Create a Test Bench for this Garage Door Controller made with VHDL to confirm th
ID: 3583149 • Letter: C
Question
Create a Test Bench for this Garage Door Controller made with VHDL to confirm this output:
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity garage_door_controller is
port (
remt, sen1, sen2, clk, rst : in std_logic;
ctr : out std_logic_vector (1 downto 0)
);
end entity;
architecture moore_fsm of garage_door_controller is
type state is (closed1, closed2, opening1, opening2, open1, open2, closing1, closing2);
signal pr_state, nx_state : state;
begin
--FSM state register:
process (clk, rst)
begin
if rst = '1' then
pr_state <= closed1;
elsif rising_edge(clk) then
pr_state <= nx_state;
end if;
end process;
--FSM combinational logic
process (pr_state, remt, sen1, sen2)
begin
case pr_state is
when closed1 =>
ctr <= "0-";
if remt = '0' then
nx_state <= closed2;
else
nx_state <= closed1;
end if;
when closed2 =>
ctr <= "0-";
if remt = '1' then
nx_state <= opening1;
else
nx_state <= closed2;
end if;
when opening1 =>
ctr <= "10";
if sen1 = '1' then
nx_state <= open1;
elsif remt = '0' then
nx_state <= opening2;
else
nx_state <= opening1;
end if;
when opening2 =>
ctr <= "10";
if remt = '1' or sen1 = '1' then
nx_state <= open1;
else
nx_state <= opening2;
end if;
when open1 =>
ctr <= "0-";
if remt = '0' then
nx_state <= open2;
else
nx_state <= open1;
end if;
when open2 =>
ctr <= "0-";
if remt = '1' then
nx_state <= closing1;
else
nx_state <= open2;
end if;
when closing1 =>
ctr <= "11";
if sen2 = '1' then
nx_state <= closed1;
elsif remt = '0' then
nx_state <= closing2;
else
nx_state <= closing1;
end if;
when closing2 =>
ctr <= "11";
if remt = '1' or sen2 = '1' then
nx_state <= closed1;
else
nx_state <= closing2;
end if;
end case;
end process;
end architecture;
Name rst clk remt sen1 sen2 pr. state C ctr 600,0 ns 1.0 us 0 ps 200,0 ns 400,0 ns 800,0 ns closed 1 closed 2 opening 1 bpening 2 open 1 l open2 I closing 1 closed 1Explanation / Answer
use IEEE.STD_LOGIC_1164.ALL;
entity garage_door_controller is
port (
remt, sen1, sen2, clk, rst : in std_logic;
ctr : out std_logic_vector (1 downto 0)
);
end entity;
architecture moore_fsm of garage_door_controller is
type state is (closed1, closed2, opening1, opening2, open1, open2, closing1, closing2);
signal pr_state, nx_state : state;
begin
--FSM state register:
process (clk, rst)
begin
if rst = '1' then
pr_state <= closed1;
elsif rising_edge(clk) then
pr_state <= nx_state;
end if;
end process;
--FSM combinational logic
process (pr_state, remt, sen1, sen2)
begin
case pr_state is
when closed1 =>
ctr <= "0-";
if remt = '0' then
nx_state <= closed2;
else
nx_state <= closed1;
end if;
when closed2 =>
ctr <= "0-";
if remt = '1' then
nx_state <= opening1;
else
nx_state <= closed2;
end if;
when opening1 =>
ctr <= "10";
if sen1 = '1' then
nx_state <= open1;
elsif remt = '0' then
nx_state <= opening2;
else
nx_state <= opening1;
end if;
when opening2 =>
ctr <= "10";
if remt = '1' or sen1 = '1' then
nx_state <= open1;
else
nx_state <= opening2;
end if;
when open1 =>
ctr <= "0-";
if remt = '0' then
nx_state <= open2;
else
nx_state <= open1;
end if;
when open2 =>
ctr <= "0-";
if remt = '1' then
nx_state <= closing1;
else
nx_state <= open2;
end if;
when closing1 =>
ctr <= "11";
if sen2 = '1' then
nx_state <= closed1;
elsif remt = '0' then
nx_state <= closing2;
else
nx_state <= closing1;
end if;
when closing2 =>
ctr <= "11";
if remt = '1' or sen2 = '1' then
nx_state <= closed1;
else
nx_state <= closing2;
end if;
end case;
end process;
end architecture;