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CSC 332 Fall 2017 9:15 AM class Quizl 300 Points Q1. 150 Points consider the int

ID: 3590606 • Letter: C

Question


CSC 332 Fall 2017 9:15 AM class Quizl 300 Points Q1. 150 Points consider the interrupt mechanism we discussed in class. the cpu Suppose we make the following change. When interrupt occurs, saves PC, PSW values in a fixed location in memory (not on the con stack). The service routine, before executing the RTI, will push those old PC, PSw values o nto the control stack, so that RTI works as usual. There are no other changes Will this scheme work? YES or NO, and then explain in less than 50 words. Q2. 150 Points Consider the following code. int i-40; cobegin s21 while i-40) S11 while (i-40) S12: i- i 1: S22: i-i1: coend print(ili What are all the possibilities regarding the output from this program for each complete (possibly infinite) execution run? Give a scenario for each such possibility.

Explanation / Answer

Q1. ANSWER:

The perform of coming back from an interrupt, for instance , via the RTI instruction, can 'automatically' cause the previous laptop and standing register values to be fixed.

Note: coming back from the interrupt handler doesn't clear the interrupt event unfinished indication, therefore the interrupt handler, before exiting has to modify the acceptable register otherwise the flow of execution can like a shot re enter the interrupt handler.

The interrupt handler needs to, upon entry, push the other registers that it modifies and, once able to exit, restore them.

Only interrupts of a lower priority area unit blocked by the interrupt event amusing the laptop to the acceptable interrupt handler. Blocked, not disabled. on some CPUs, for example most DSPs, there also are code interrupts which will be triggered by AN process. this can be typically employed by hardware interrupt handlers to trigger the info process when some quantity of knowledge has been input/saved during a buffer. This separates the I/O from the process thereby sanctionative the hardware interrupt event handler to be fast and still have the info processed during a timely way