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Show work!! (Use separate sheets if necessary) Name_AdaiA BRuN Fill in the reque

ID: 3596169 • Letter: S

Question

Show work!! (Use separate sheets if necessary) Name_AdaiA BRuN Fill in the requested register contents and flag status' as if the instructions were executed on the Z80 microprocessor. B (Hex) B (Dec) S Z CY LDB. 62H- SRA B SRA B (Signed Number) 2. LD B, 84H SRA B SRA B LD B, 16H SLA B SLAB LD DE, COUNT I 4. Compute delay time both including and excluding the instruction outside the loop for: a) COUNT=0 b) COUNT= 1 DLOOP: DEC DE LDA, E 4 OR D4 JP NZ, DLOOP IO f=3MHz LD D, OCOUNT LD E, lCOUNT NOP 4 DEC Ey JP NZ, ILOOP 1o NOP 4 5. Compute ICOUNT so that inner loop delay is .1 msec. LOOP: LOOP: 6. Compute OCOUNT so that total delay is 20 msec. T 500 nsec DEC D JP NZ, OLOOP IO WWEllI

Explanation / Answer

Z80 instruction definition and architecture is defined.

1)

LD B 62H

This is a load instrcuction and it will load the values into B which is 62 in hexadecimal.

So a value of 62 will be loaded into B.

B (Hex) will be 62

B (dec) will be 98

S - 0 (There is no sign change with operation)

Z - 0 (zero flag no change)

Carry flag (CY) - 0 (no change in carry)

SRA instrcution means arithemtic shift right. In this bit 7 remains unchanged and others bits are shited right by 1 and 0th bit is moved to carry flag.

Now B has 62 value which means 0110 0010

SRA B instruction result will be

B (hex) will be 31 (right shift means it will be divided by 2)

B (dec) will be 49 (again right shift)

S - 0

Z - 0 (zero flag is zero)

CY - 0 ( bit 0 moved to carry flag)

Again SRA B instruction is executed.

B has 31 value in hex which means in binary 0011 0001

Now SRA result will be

B(Hex) will be 18 (Right shift by 1)

B (decimal) will be 24

S flag will be 0

C - 0

CY - 1( as the last bit was 1 before the operation)

2)

Z80 instruction definition and architecture is defined.

1)

LD B 84H

This is a load instrcuction and it will load the values into B which is 84 in hexadecimal.

So a value of 84 will be loaded into B.

B (Hex) will be 84

B (dec) will be 132

S - 1 (MSB is set for this number)

Z - 0 (zero flag no change)

Carry flag (CY) - 0 (no change in carry)

SRA instrcution means arithemtic shift right. In this bit 7 remains unchanged and others bits are shited right by 1 and 0th bit is moved to carry flag.

Now B has 84 value which means 1000 0100

SRA B instruction result will be

B (hex) will be C2 (right shift means it will be divided by 2 but sign will remain as it is so it will be 1100 0010)

B (dec) will be 194 (again right shift)

S - 1

Z - 0 (zero flag is zero)

CY - 0

Again SRA B instruction is executed.

B has C2 value in hex which means in binary 1100 0010

Now SRA result will be

B(Hex) will be A1 (Right shift by 1 after shift 1010 0001)

B (decimal) will be 161

S flag will be 1

C - 0

CY - 0

3)

Z80 instruction definition and architecture is defined.

LD B 16H

This is a load instrcuction and it will load the values into B which is 16 in hexadecimal.

So a value of 16 will be loaded into B.

B (Hex) will be 16

B (dec) will be 22

S - 0 (MSB is set for this number)

Z - 0 (zero flag no change)

Carry flag (CY) - 0 (no change in carry)

SLA instrcution means arithemtic shift left. In this bit 7 remains unchanged and others bits are shited left by 1 and 7th bit is moved to carry flag.

Now B has 16 value which means 0001 0110

SLA B instruction result will be

B (hex) will be 2C (left shift means it will be multiplied by 2 but sign will remain as it is so it will be 0010 1100)

B (dec) will be 44 (again left shift)

S - 0

Z - 0 (zero flag is zero)

CY - 0 (bit 7th is moved to carry flag)

Again SLA B instruction is executed.

B has 2C value in hex which means in binary 0010 1100

Now SLA result will be

B(Hex) will be 58 (left shift by 1 after shift 0101 1000)

B (decimal) will be 88

S flag will be 0

Z - 0

CY - 0 ( as the 7th bit was 0 before the operation)

The numbers in the loop are coming from the instruction execution time and the carry flag criteria. This is calculated bsaed on the overflow.