For the below set of instructions, assume a 5 stage pipeline as we have been lea
ID: 3598624 • Letter: F
Question
For the below set of instructions, assume a 5 stage pipeline as we have been learning in chapter 4, assume that there is no hardware forwarding or hazard detection. The piler/assembler must insert nops Where the data hazard exists to insure the correct answer a Rewrite the code by inserting nop(s) in the proper location to insure the correct result (ONE ASSEMBLY INSTRUCTION PER BLANK THERE MAY BE MORE BLANKS THAN REQUIRED LINES OF ASSEMBLY) addi x2, x2,-2 w x5, 02) If the 5-stage pipeline now added forwarding from the MEMWB pipeline register with no hardware data hazard detection, rewrite the assembhy with the appropriate NOPs where required to insure proper operation. ONE ASSEMBLY INSTRUCTION PER BLANK THERE MAY BE MORE BLANKS THAN REQUIRED LINES OF ASSEMBLY) If the 5-stage pipeline now added forwarding from both the EXMEM and the MEMWB pipeline registers with no hardware data hazard detection, rewrite the assembly with the appropriate NOPs where required to insure proper operation. ONE ASSEMBLY INSTRUCTION PER BLANK THERE MAY BE MORE BLANKS THAN REQUIRED LINES OF ASSEMBLY)Explanation / Answer
a)
In the first sequence of instructions there is a data hazard between addi and lw instruction where the result of x2 is required in the lw (load) instruction. Also there is another data hazard with x5 register where the result of x5 is used in next load instruction in x6. So we will need two nops in between both the instructions to counter the data hazard so that results are available.
The code will be:
addi x2,x2,-2
nop
nop
lw x5,0(x2)
nop
nop
lw x6,4(x5)
b)
We are adding a MEM WB forwarding in our CPU. This means that the write back values are always forwarded to the MEM stage. This will solve our load load hazard case since the value in write back will be forwarded to the mem stage.
so the code will become
addi x2,x2,-2
nop
nop
lw x5,0(x2)
lw x6,4(x5)
c)
In this case we are doing forwarding in EX MEM stage as well. so any value in memory stage will be forwarded to the execute stage as well. This will solve for addi problem as when the instruction is in mem stage it's value will be passed to the execute stage and same can be used by next lw instruction. code will be
addi x2,x2,-2
lw x5,0(x2)
lw x6,4(x5)