Problem 1: A 32 KB direct-mapped data cache uses a victim cache that stores the
ID: 3605647 • Letter: P
Question
Problem 1: A 32 KB direct-mapped data cache uses a victim cache that stores the most recently discarded two blocks. On a cache miss, the victim cache is examined and if the item is found there, then the block is swapped with the associated block in the cache. This provides a small degree of associativity. The direct-mapped cache has a hit time of 1 cycle, the victim cache takes a further 1 cycle for access and if found, 1 cycle to swap. If the item is not in the victim cache, the extra cycle for the swap does not take place. The cache has a miss penalty of 40 cycles (main memory access). Assume that 5% of all misses are actually found in the victim cache. Compare the direct-mapped cache with victim cache to the same sized 2-way set associative cache (without victim cache), which also has a hit time of 1 cycle - which one should we use? Explain why Miss rate components Cache size (KB) Degree associative |Total miss rate 1-wa Z-wa 4-wa 8-wa Compuls Conflict 32 32 32 32 0.042 0.038 0.037 0.037 | 0.000 | | 0.2% | 0.037 | 89% | 0.005 | 11% 0.0001 0.2% 0.037 | 99% | 0.000 | 0% | 100% | 0.000 | 0% | | 0.0001 0.2% 0.037 | 0.0001 | 0.2% | 0.037 | 100% | 0.000 | 0%Explanation / Answer
The miss rates are:
The solution is:
First, we findout the miss penalty in terms of clock cycles: 100 ns/5 ns = 40 cycles.
For the direct-mapped data cache is (1 + 0.024 x 40) = 1.96 cycles.
For data accesses by victim cache, which occur on about 5% of all misses, the penalty is (3 + 0.024 x 40) = 3.96 cycles per access, or 0.19 cycles per instruction.
The total penalty is 2.15 CPI .
In the 2-way set associative penalty is (1 + 0.038 x 40) = 2.52 CPI.
The total penalty is 0.45 CPI .
In this case, the 2-way set associative performs better because of the lack of a stall on data accesses.