I have this problem for my homework. I tried solving it angot 15 cycles for part

Question

I have this problem for my homework. I tried solving it angot 15 cycles for part A and 12 for part B but am really unsuresince im not sure how forwarding and bypassing play inexactly. I would appreciate some help with this. Thanks.

Use the following code fragment and assume that the initial valueof R4 is R2+792.

Loop LD F0, 0(R2)
LD F4, 0(R3)
MULTD F0, F0, F4
ADDD F2, F0, F2
ADDI R2, R2, #8
ADDI R3, R3, #8
SUB R5, R4, R2
BNEZ R5, Loop

Using the RISC five-stage pipeline and assuming all memory accessestake 1 (one) clock cycle, please answer the following:

a) Show the timing of this instruction sequence for the pipelinewithout any forwarding or bypassing
hardware but assuming a register read and writes in the same clockcycle ‘forwards’ through the register
file. Use the following pipeline chart. Assume that branch ishandled by flushing the pipeline. If all
memory references hit in the cache, how many cycles does this looptake to execute?

b) Show the timing of the instruction sequence for the pipelinewith normal forwarding and bypassing
hardware. Use the given pipeline chart. Assume that the branch ishandled by predicting it as not taken. If all memory references hitin the cache, how many cycles does this loop take to execute?

Explanation / Answer

Yea for part B it will be 12 as branch is predicted not to be taken (i did not read the question completely)

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