Consider the following seven example assembly instructions discussed in class: L
ID: 3662213 • Letter: C
Question
Consider the following seven example assembly instructions discussed in class: LDA x, STA x, ADD x, NAND x, SHFT, J x, and BNE x. Suppose we want to implement these instructions on the pseudo-CPU discussed in class (shown below). An instruction consist of 16 bits: A 4-bit opcode and a 12-bit address. PC and MAR each contain 12 bits. AC and MDR each contain 16 bits, and IR is 4 bits. All operands are 16 bits. Give the sequence of microoperations required to implement the Fetch cycle, which is common for all five instructions. Give the sequence of microoperations required to implement the Execute cycle for each of the five instructions given above. Your solutions result in minimum number of microoperations.Explanation / Answer
Instruction codes
we examine the sequences of microoperations that the Basic Computer goes through for each instruction. Here, you should begin to understand how the required control signals for each state of the CPU are determined, and how they are generated by the control unit.
The CPU performs a sequence of microoperations for each instruction. The sequence for each instruction of the Basic Computer can be refined into 4 abstract phases:
1. Fetch instruction
2. Decode
3. Fetch operand
4. Execute
Program execution can be represented as a top-down design:
1. Program execution
a. Instruction 1
i. Fetch instruction
ii. Decode
iii. Fetch operand
iv. Execute
b. Instruction 2
i. Fetch instruction
ii. Decode
iii. Fetch operand
iv. Execute
c. Instruction 3 ...
Program execution begins with:
PC address of first instruction, SC 0
After this, the SC is incremented at each clock cycle until an instruction is completed, and then it is cleared to begin the next instruction. This process repeats until a HLT instruction is executed, or until the power is shut off.
Instruction Fetch and Decode
The instruction fetch and decode phases are the same for all instructions, so the control functions and microoperations will be independent of the instruction code.
Everything that happens in this phase is driven entirely by timing variables T0, T1 and T2. Hence, all control inputs in the CPU during fetch and decode are functions of these three variables alone.
T0: AR PC
T1: IR M[AR], PC PC + 1
T2: D0-7 decoded IR(12-14), AR IR(0-11), I IR(15)
For every timing cycle, we assume SC SC + 1 unless it is stated that SC 0.
The operation D0-7 decoded IR(12-14) is not a register transfer like most of our microoperations, but is actually an inevitable consequence of loading a value into the IR register. Since the IR outputs 12-14 are directly connected to a decoder, the outputs of that decoder will change as soon as the new values of IR(12-14) propagate through the decoder.
Note that incrementing the PC at time T1 assumes that the next instruction is at the next address. This may not be the case if the current instruction is a branch instruction. However, performing the increment here will save time if the next instruction immediately follows, and will do no harm if it doesn't. The incremented PC value is simply overwritten by branch instructions.
In hardware development, unlike serial software development, it is often advantageous to perform work that may not be necessary. Since we can perform multiple microoperations at the same time, we might was well do everything that might be useful at the earliest possible time.
Likewise, loading AR with the address field from IR at T2 is only useful if the instruction is a memory-reference instruction. We won't know this until T3, but there is no reason to wait since there is no harm in loading AR immediately.
Figure 5-8 shows part of the implementation of the CPU for the first two clock pulses of the instruction cycle. Note that each control input for the bus, registers, and ALU is a Boolean function with multiple terms. Hence, the OR gates in the diagram.
Instruction Fetch and Decode
The instruction fetch and decode phases are the same for all instructions, so the control functions and microoperations will be independent of the instruction code.
Everything that happens in this phase is driven entirely by timing variables T0, T1 and T2. Hence, all control inputs in the CPU during fetch and decode are functions of these three variables alone.
T0: AR PC
T1: IR M[AR], PC PC + 1
T2: D0-7 decoded IR(12-14), AR IR(0-11), I IR(15)
For every timing cycle, we assume SC SC + 1 unless it is stated that SC 0.
The operation D0-7 decoded IR(12-14) is not a register transfer like most of our microoperations, but is actually an inevitable consequence of loading a value into the IR register. Since the IR outputs 12-14 are directly connected to a decoder, the outputs of that decoder will change as soon as the new values of IR(12-14) propagate through the decoder.
Note that incrementing the PC at time T1 assumes that the next instruction is at the next address. This may not be the case if the current instruction is a branch instruction. However, performing the increment here will save time if the next instruction immediately follows, and will do no harm if it doesn't. The incremented PC value is simply overwritten by branch instructions.
In hardware development, unlike serial software development, it is often advantageous to perform work that may not be necessary. Since we can perform multiple microoperations at the same time, we might was well do everything that might be useful at the earliest possible time.
Likewise, loading AR with the address field from IR at T2 is only useful if the instruction is a memory-reference instruction. We won't know this until T3, but there is no reason to wait since there is no harm in loading AR immediately.
Figure 5-8 shows part of the implementation of the CPU for the first two clock pulses of the instruction cycle. Note that each control input for the bus, registers, and ALU is a Boolean function with multiple terms. Hence, the OR gates in the diagram.
Instruction Fetch and Decode
The instruction fetch and decode phases are the same for all instructions, so the control functions and microoperations will be independent of the instruction code.
Everything that happens in this phase is driven entirely by timing variables T0, T1 and T2. Hence, all control inputs in the CPU during fetch and decode are functions of these three variables alone.
T0: AR PC
T1: IR M[AR], PC PC + 1
T2: D0-7 decoded IR(12-14), AR IR(0-11), I IR(15)
For every timing cycle, we assume SC SC + 1 unless it is stated that SC 0.
The operation D0-7 decoded IR(12-14) is not a register transfer like most of our microoperations, but is actually an inevitable consequence of loading a value into the IR register. Since the IR outputs 12-14 are directly connected to a decoder, the outputs of that decoder will change as soon as the new values of IR(12-14) propagate through the decoder.
Note that incrementing the PC at time T1 assumes that the next instruction is at the next address. This may not be the case if the current instruction is a branch instruction. However, performing the increment here will save time if the next instruction immediately follows, and will do no harm if it doesn't. The incremented PC value is simply overwritten by branch instructions.
In hardware development, unlike serial software development, it is often advantageous to perform work that may not be necessary. Since we can perform multiple microoperations at the same time, we might was well do everything that might be useful at the earliest possible time.
Likewise, loading AR with the address field from IR at T2 is only useful if the instruction is a memory-reference instruction. We won't know this until T3, but there is no reason to wait since there is no harm in loading AR immediately.
Figure 5-8 shows part of the implementation of the CPU for the first two clock pulses of the instruction cycle. Note that each control input for the bus, registers, and ALU is a Boolean function with multiple terms. Hence, the OR gates in the diagram.