I really need some help understaning how system verilog coding works in Cygwin I
ID: 3663006 • Letter: I
Question
I really need some help understaning how system verilog coding works in Cygwin
I am a PC user, so I in order to have a linux version or an option to run commands I installed a program called Cygwin. This program currently allows me to run .cpp file and supposedly to run verilog (.v) and systemVerilog (.sv) file, but I am not able to or familiar with how to command call them from Cygwins terminal. I would also like to testbech each file that I run.
Online I found a system called edaplayground.com that allows you to implement your design and also testbench your work. I'm a novice at coding so I really need some guidance and the following quesitons answered.
1. Can Cygwin truly run and open .sv file? If so, what are the commands to do this. Also, how do I run the testbench with this?
2. If # one is false, do you recommend the above online compiler or are there other free/better versions available?
3. As a begginer, where should I start when learning systemverilog and also learning how to run testbench code?
Explanation / Answer
Any information needed please comment
3)
>To start with, keep it simple and study the book SystemVerilog for Verification by Chris Spear. Then you can go through the System Verilog LRM for detailed syntax. You can refer the website WWW.TESTBENCH.IN as well.
>There are couple of Sites which I know
http://systemverilog.in/
http://www.testbench.in/
How to Run Testbench code:
Use:
$ iverilog -o ripple ripple_carry_adder.v ripple_carry_adder_tb.v
$ vvp ripple
to compile and run your code in terminal. You might add a $monitor to your testbench to be able to print some more results than just errors.