Please give full answer. Consider the following assembly language code: I0: ADD
ID: 3678275 • Letter: P
Question
Please give full answer.
Consider the following assembly language code: I0: ADD R4 = R1 + R0; I1: SUB R9 = R3 - R4; I2: ADD R4 = RS + R6; I3: LDW R2 = MEM[R3+ 100]; I4: LDW R2 = MEM[R2 + 0]; I5: STW MEM[R4 + 100] = R2; I6: AND R2= R2 & Rl; I7: BEQ R9 == Rl, Target; I8: AND R9= R9 & Rl; Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5- stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below (instructions on the left, cycles on top) for the code. Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding unit detects (arrow between the stages handing off the data and the stages receiving the data). What is the final execution time of the code?Explanation / Answer
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
I0 IF ID EX MEM WB
I1 IF ID EX MEM WB
I2 IF ID EX MEM WB
I3 IF ID EX MEM WB
I4 IF ID X EX MEM WB
I5 IF X ID EX MEM WB
I6 X IF ID EX MEM WB
I7 IF ID EX MEM WB
I8 IF ID EX MEM WB
i unable table instruction 8 should ends at T13.
INSTRUCTION PIPELINING
As computer systems evolve, greater performance can be achieved by taking advantage of
improvements in technology, such as faster circuitry, use of multiple registers rather than a single
accumulator, and the use of a cache memory. Another organizational approach is instruction pipelining in
which new inputs are accepted at one end before previously accepted inputs appear as outputs at the other
end.
Figure 3.1a depicts this approach. The pipeline has two independent stages. The first stage fetches an
instruction and buffers it. When the second stage is free, the first stage passes it the buffered instruction.
While the second stage is executing the instruction, the first stage takes advantage of any unused memory
cycles to fetch and buffer the next instruction. This is called instruction prefetch or fetch overlap.
This process will speed up instruction execution only if the fetch and execute stages were of equal
duration, the instruction cycle time would be halved. However, if we look more closely at this pipeline
(Figure 3.1b), we will see that this doubling of execution rate is unlikely for 3 reasons:
1 The execution time will generally be longer than the fetch time. Thus, the fetch stage may have
to wait for some time before it can empty its buffer.
2 A conditional branch instruction makes the address of the next instruction to be fetched
unknown. Thus, the fetch stage must wait until it receives the next instruction address from the execute
stage. The execute stage may then have to wait while the next instruction is fetched.
3 When a conditional branch instruction is passed on from the fetch to the execute stage, the fetch
stage fetches the next instruction in memory after the branch instruction. Then, if the branch is not taken,
no time is lost .If the branch is taken, the fetched instruction must be discarded and a new instruction
fetched.
To gain further speedup, the pipeline must have more stages. Let us consider the following
decomposition of the instruction processing.
1. Fetch instruction (FI): Read the next expected instruction into a buffer.
2. Decode instruction (DI): Determine the opcode and the operand specifiers.