Consider the sequence of memory accesses from the previous exercise as above. No
ID: 3690561 • Letter: C
Question
Consider the sequence of memory accesses from the previous exercise as above. Now, the 3 processors are connected with a point-to-point interconnect and implement a distributed shared memory with a directory-based write-invalidate cache coherence protocol. For every memory access, describe the messages that are sent on the network and the state of the block in the caches and in the directory using the following template.
Consider the following assumptions:
? A message only accommodates one address or one data word.
Home nodes for memory locations X and Y are both associated with processor P1 and that a transfer between this home memory and the P1-cache does not result in traffic on the point- to-point interconnect.
? Caches are direct-mapped and each cache block stores only one word
? Words X and Y map to the same cache block in each block (i.e. X and Y can’t co-exist in a
cache at any time).
? Memory locations X and Y are not in any of the caches at the start of the sequence
Explanation / Answer
Underline indicate that the messages are local
– they will not be transmitted by the interconnect network