The following statement show its ARM assembler machine code as the following: AN
ID: 3698437 • Letter: T
Question
The following statement show its ARM assembler machine code as the following: AND R2, R2, 8xFFFFFFFD ARM assembler code: 00001008: E3C22002 AND R1, R1, 0xFFFFFFFD Questions 1. Is the above statement is valid ARM instruction? [1] 2. For the both answers in 1 (valid or non-valid), explain why? [1] 3. Is this a pseudo-instruction? [1)] 4. Justify (The Data processing instruction format is shown below. [1] 31 2825 20 6 15 12 11 Rd -Operation Code 0100 ADD 1000-TST 1100-ORR 0101-ADC 1001-TEQ1101 MOV 0110-SBC 1010 CMP 1110 BIC 0111 -RSC 1011-CMN 1111 MVN 0000 AND 010 -SUB 0011- RSBExplanation / Answer
1.Yes it is a valid ARM instruction.
2.This is a logical AND ARM instruction which follows offset addressing mode.This is an immediate addressing operation where the value of AND operation os stored in the register R1.The operands are R1 and the offset value given.
3.Yes the above is a pseudo instruction .As the instruction itself is 32 bit a 32 bit value cannot be loaded directly due to which a pseudo instruction comes into play
4.The condition field is responsible to determine whether the CPU will execute the instruction.This field is followed by 3 bits 001 which india te that it is a data processing instruction.The op code field is a set of 4 bits which determine the type of operation to be performed on the operands.Here the operands are registers rn rd and operand 2 which is of 12 bits.To cause the condition flag to be updated s bit needs to be set by post fixing the instruction.