Part 4: Multiprocessor Question 7 (15 pt). A 4-way SMP configuration implements
ID: 3702257 • Letter: P
Question
Part 4: Multiprocessor
Question 7 (15 pt). A 4-way SMP configuration implements write-back cache using the MESI (Modified Exclusive Shared Invalid) algorithm for cache coherency. Assume that location 1E0 is not in any cache at the start of the following sequence. Show the state (M, E, S or I) for the line containing location 1E0 in each processor cache and the state in main memory after each operation. Also note any transfers to/from memory if any occur.
For example, if Px has a snoop hit of Py reading a line while it is holding a dirty copy of the line, indicate “Px writes lineback, Py reads line” under the Memory Transfers column.
a) Processor 0 reads from location 1E0.
b) Processor 0 writes to location 1E0.
c) Processor 1 reads from location 1E0.
d) Processor 2 reads from location 1E0.
e) Processor 1 writes to location 1E0.
f) Processor 3 writes to location 1E0
Action P0 P1 P2 P3 Mem Memory Transfers P0 Reads P0 Writes P1 Reads P2 Reads P1 Writes P3 WritesExplanation / Answer
Action
P0
P1
P2
P3
Mem
Memory Transfers
P0 Reads
E
I
I
I
V
P0 reads line
P0 Writes
M
I
I
I
I
P1 Reads
S
S
I
I
V
P0 writes line back, P1 reads line.
P2 Reads
S
S
S
I
V
P2 reads line
P1 Writes
I
M
I
I
I
P3 Writes
I
I
I
M
I
P1 writes line back, P3 reads line.
Action
P0
P1
P2
P3
Mem
Memory Transfers
P0 Reads
E
I
I
I
V
P0 reads line
P0 Writes
M
I
I
I
I
P1 Reads
S
S
I
I
V
P0 writes line back, P1 reads line.
P2 Reads
S
S
S
I
V
P2 reads line
P1 Writes
I
M
I
I
I
P3 Writes
I
I
I
M
I
P1 writes line back, P3 reads line.