Consider a two-level cache. In 1000 memory references, there are 50 misses in th
ID: 3702767 • Letter: C
Question
Consider a two-level cache. In 1000 memory references, there are 50 misses in the first level and 10 misses in the second level. Assume the hit time of LI is l cycle, the hit time of L2 is 10 clock cycles, the miss penalty from the L2 cache to memory is 500 cycles, and there are 1.3 memory references per instruction. No need to consider write operations in this problem. a) What are the local miss rate for L1? b) What is the local miss rate for L2? c) What is the global miss rate of the d) What is the average memory access time of the two-level cache in cycles? e) What is the average stall cycles per instruction? two-level cache?Explanation / Answer
Local miss rate for L1= Misses in L1/ Total memory references
=50/1000= 0.05
Local miss rate for L2= Miss in L2/ Miss in L1 = 10/50= 0.2
Global miss rate of two level cache= Local miss rate for L1 * Local miss rate in L2 = 0.05*0.2= 0.01
Average memory access time of two level cache in cycles = hit time of L1 + miss rate of L1 * (hit time of L2 + miss rate of L2 * miss penalty of L2) = 1+0.05(10+0.2*500) = 6.5 cycles
Average stall cycles per instruction= (Memory access/Instruction) * (miss/memory access) * (cycles/miss)
Average stall cycles per instruction= stalls due to L1 miss + stalls due to L2 miss
=( 1.3*50/1000*10) + (1.3 * 10/1000*500)= 7.15