Cache Memory Put the cache interactions in the proper order (you can use the lef
ID: 3703976 • Letter: C
Question
Cache Memory
Put the cache interactions in the proper order (you can use the left column to order your answers, write the letters in order in the boxes at the bottom):
A. The L2 cache controller determines the cache set, the requested cache tag and the block offset
B. L1 cache receives a block from the L2 cache controller
C. L2 cache checks for an empty block in the set
D. L1 cache identifies the byte field in the L1 cache cache block and returns it to the CPU
E. L2 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request
F. No empty block in L2 cache set
G. L3 cache set tag match
H. L1 cache sends the L2 cache controller a memory address
I. L2 cache writes the block data, LRU info and cache tag to the cache block
J. The CPU sends the L1 cache controller a memory address
K. L2 cache sends the L3 cache controller a memory address
L. The L2 cache Controller determines the least recently used block entry
M. L2 cache identifies the byte field in the L2 cache cache block and returns it to L1 cache
N. No empty block in L1 cache set
O. The L3 cache controller determines the cache set, the requested cache tag and the block offset
P. The L1 cache Controller determines the least recently used block entry
Q. L3 cache identifies the byte field in the L3 cache cache block and returns it to L2 cache
R. L1 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request
S. The L1 cache controller determines the cache set, the requested cache tag and the block offset
T. L2 cache receives a block from the L3 cache controller
U. L1 cache writes the block data, LRU info and cache tag to the cache block
V. No L2 cache set tag match
W. L1 cache checks for an empty block in the set
X. L3 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request
Y. No L1 cache set tag match
A. The L2 cache controller determines the cache set, the requested cache tag and the block offset
B. L1 cache receives a block from the L2 cache controller
C. L2 cache checks for an empty block in the set
D. L1 cache identifies the byte field in the L1 cache cache block and returns it to the CPU
E. L2 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request
F. No empty block in L2 cache set
G. L3 cache set tag match
H. L1 cache sends the L2 cache controller a memory address
I. L2 cache writes the block data, LRU info and cache tag to the cache block
J. The CPU sends the L1 cache controller a memory address
K. L2 cache sends the L3 cache controller a memory address
L. The L2 cache Controller determines the least recently used block entry
M. L2 cache identifies the byte field in the L2 cache cache block and returns it to L1 cache
N. No empty block in L1 cache set
O. The L3 cache controller determines the cache set, the requested cache tag and the block offset
P. The L1 cache Controller determines the least recently used block entry
Q. L3 cache identifies the byte field in the L3 cache cache block and returns it to L2 cache
R. L1 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request
S. The L1 cache controller determines the cache set, the requested cache tag and the block offset
T. L2 cache receives a block from the L3 cache controller
U. L1 cache writes the block data, LRU info and cache tag to the cache block
V. No L2 cache set tag match
W. L1 cache checks for an empty block in the set
X. L3 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request
Y. No L1 cache set tag match
Explanation / Answer
10 A. The L2 cache controller determines the cache set, the requested cache tag and the block offset 24 B. L1 cache receives a block from the L2 cache controller 13 C. L2 cache checks for an empty block in the set 25 D. L1 cache identifies the byte field in the L1 cache cache block and returns it to the CPU 11 E. L2 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request 14 F. No empty block in L2 cache set 20 G. L3 cache set tag match 9 H. L1 cache sends the L2 cache controller a memory address 16 I. L2 cache writes the block data, LRU info and cache tag to the cache block 1 J. The CPU sends the L1 cache controller a memory address 17 K. L2 cache sends the L3 cache controller a memory address 15 L. The L2 cache Controller determines the least recently used block entry 23 M. L2 cache identifies the byte field in the L2 cache cache block and returns it to L1 cache 6 N. No empty block in L1 cache set 19 O. The L3 cache controller determines the cache set, the requested cache tag and the block offset 7 P. The L1 cache Controller determines the least recently used block entry 21 Q. L3 cache identifies the byte field in the L3 cache cache block and returns it to L2 cache 3 R. L1 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request 2 S. The L1 cache controller determines the cache set, the requested cache tag and the block offset 22 T. L2 cache receives a block from the L3 cache controller 8 U. L1 cache writes the block data, LRU info and cache tag to the cache block 12 V. No L2 cache set tag match 5 W. L1 cache checks for an empty block in the set 18 X. L3 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request 4 Y. No L1 cache set tag match