Assume that one implementation of the original MIPS ISA can run at 1 GHz. We wan
ID: 3709531 • Letter: A
Question
Assume that one implementation of the original MIPS ISA can run at 1 GHz. We want to modify the MIPS ISA and architecture design. For the same given code and data, our new design
increases the instruction count by 10% but reduces the average CPI by 20% . How fast (i.e., at what clock frequency) must our new design run in order to achieve a speedup of 4 compared with the original implementation? Show your work. (Hint: You don't need to solve the previous problems in order to solve this one.)
Please show work and eqautions uses
Explanation / Answer
The clock frequency of original MIPS ISA = 1 GHz = 109 Hz
Therefore number of clock cycle in 1 second = 109
Therefore time needed to execute 1 clock cycle = 1/ 109 second.
Let the number of instruction in this be x and CP1 =y
Therefore time needed to execute x instructions = x*CPI*clock cycle time = x*y*(1/ 109) second = xy/109 second.
Let the clock frequency in the new design be z Hz.
Number of instructions in the new design = 1.1x
CPI of the new design = y - 0.2y = 0.8y
Therefore time taken to execute 1.1x instructions = 1.1x*0.8y*(1/z) = 0.88xy/z seconds.
Speedup = time taken by original / time taken by new design = (xy/109) / (0.88xy/z) = z/(109*0.88)
Given speedup = 4
Therefore z/(109*0.88) = 4
Therefore z = 4*0.88*109 Hz = 3.52*109 Hz = 3.52 GHz