IF = 450ps ID = 200ps EX = 400ps MEM = 250ps WB = 100ps For the above resource t
ID: 3727465 • Letter: I
Question
IF = 450ps ID = 200ps EX = 400ps MEM = 250ps WB = 100ps For the above resource timing, what is the clock cycle time/period in a 5-stage pipelined CPU implementation (in ps)? aFor the above resource timing, what is the clock cycle time/period in a single cycle CPU architecture (in ps)? based on these resources (in ps)? CPU implementation based on these resources (in ps)? datapath into two new stages, now a total of 6 stages, each with 50% the time of the original pipeline stage, which stage would you split? (IF, ID, EX, MEM, WB) instruction latency of a sub, subtract, instruction (in ps)? What is the instruction latency of an add instruction in a 5-stage pipeline CPU architecture What is the instruction latency of a nor instruction in a single cycle es lf you can split only one stage of the pipeline abs Based on this new pipeline architecture of the split above stage into 2 stages, what is the abExplanation / Answer
Solution:
There are five stages that are:
IF, ID, EX, MEM, WB,
a)
The values are IF = 450ps ID = 200 ps EX = 400ps MEM = 250ps and WB = 100ps
the clock cycle time = Fetch + Decode + Execute + Memory + Write back
=IF + ID+ EX + MEM +WB
= 450ps +200ps + 400ps + 250ps + 100ps
=1400 ps
b)
The clock cycle time/period in a single cycle CPU is
The latency is the same as cycle time.
In this process, one cycle is entering as fetching first instruction and ending with write back.
So the time taking for one cycle is 1400ps
The throughput is 1/ clock cycle time ( inst/s) that is 1/1400 = 0.00071428571 inst/s
c)
The reduced Cycle Time = longest stage + register dely.
Latency = reduced Cycle Time * s where ‘s’ is number of stages.
Each stage takes one cycle
The longest stage EX = 400ps, register delay=0 ps and there are 5 stages so s=5
The reduced Cycle Time = 400 ps + register delay =400 ps
Then latency = 5*400 ps =2000 ps
And the Throughput value is 1/2000 = 0.0005 inst/ps
d)
same above explained
e)
We will decide the longest stage to split in half(50%) that is EX=400 ps.
So the cycle time develops with 2nd longest stage length MEM=250 ps.
We can Calculate latency from 2nd longest stage length. In this time, 6 stages are involved in the system.
So, Latency =second longest stage length * 6 = 250 ps * 6 = 1500 ps
Through put is 1/1500= 0.000667 inst/ps
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