Please answer all the questions! Question 1. 12 marks] Using RTL, show the first
ID: 3740616 • Letter: P
Question
Please answer all the questions!
Question 1. 12 marks] Using RTL, show the first register transfer at the start time and indicate the start time as T1. Also, explain the process in your words Question 2. [2 marks] Using RTL, show the next register transfers which obtain the instruction from memory at time T2 Explain the use of Data Register (DR) Question 3. [2 marks] Explain the three register transfers in the following T3: {DO, ..., D7) -DEC(IR(12-14)), AR IR(0-11), I-IR(15) Question 4. 12 marks] Show the register transfers for the direct and indirect addressing in RTL using DR, AR and Memory Indicate direct addressing with T0 and indirect addressing with T1 and T2 Question 5. [ 2 marks] Write down the RTL for load and store operations. How many number of register transfers are required by both operations?Explanation / Answer
1. register to register transfer R2<- R1 is used.This means transfer value of R1 to R2.R1 and R2 are registers.
2.moving data from a memory address to the data register,we write:
Read: DR <- M[AR]
To indicate in RTL that we are moving data from Register 1 to a memory location, we write:
Write: M[AR] <- R1
3. AR and IR are registers.The given code is for enabling decoder.During the clock transition associated with timing signal T2,the operation code in IR is decoded, the indirect bit is transferred to the flip-flop1, and the address part of the instruction is transferred to AR.
4. Direct addressing
T0 + T2 : AR = (PC ^ T0) ? (IR(0-11) ^ T2)
T0+T1+T2 : SC = SC + 1
steps are,
T1 : IR = M[AR] Enable IR Load
T1: PC = PC + 1 Enable PC Increment
T2: {D7,D6,...,D1,D0} = DEC( IR(12-14) ) Enable Decoder
T2: I = IR(15) Enable I Load
I' D2 T3 : AC = M[AR] Apply AR to Address Bus MUX,
Enable AC Load
I' D2 T3: SC = 0 Enable SC Clear
Indirect addressing
T0 : AR = PC, SC = SC + 1
T1 :DR = M[AR],IR = M[AR], PC = PC + 1, SC = SC + 1
T2 : {D7,D6,...,D1,D0} = DEC( IR(12-14) ), I = IR(15), AR = IR(0-11), SC = SC + 1
I D2 T3 : DR = M[AR], SC = SC + 1
I D2 T4 : AR = DR(0-11), SC = SC +1
I D2 T5 : AC = M[AR], SC = 0
5. load operation
MAR ? X # load X (address) into MAR
MBR ? M[MAR] # load value stored at address into MBR
AC ? MBR # load value in MBR into AC
3 transfers are required.x to mar,load to mbr and load mbr to ac.Here Load X loads the value from address X into the AC
store operation
MAR ? X # load address into MAR
MBR ? AC # load AC value into MBR
M[MAR] ? MBR # write MBR value into the Memory of the address indicated by the MAR
In this also 3 transfer operations are required.Here Store X stores the current value from the AC into address X