Consider the following primitive compute r: MUX MAR load MEM w(d) enable o- (e)

Question

Consider the following primitive compute r: MUX MAR load MEM w(d) enable o- (e) bus PC MUX MBR load (g) IR (h) -o load 3 21 O S-O) MUX So0) AR load-(k) BR loado-l) ALU The output of the memory MEM is "enabled" when the control input (e) is set to "low". A "read" operation is performed when the control input (d) is "high" The program counter PC will be "incremented" by 1 when the control bit (a) is "low." The registers IR, MAR, MBR, AR, and BR will perform the "load" operation when the control bits (h), (c), (g), (k), and (1) are "low," correspondingly The ALU has 4 operations, encoded into two control bits, as follows n operation 0 0 0 transfer A 1 transfer B 0 A- A+B

Explanation / Answer

MAR<-PC

MBR<-MEM[MAR], PC<-PC+1

IR<-MBR

1st : PC<-PC+1, IR<- MBR, AR<- IR, A<-AR,B<-BR, A-B opertion

2nd: PC<-PC+1, A-B

3rd:MBR<-MEM[MAR],IR<-MBR,transferA

a b c d e f g h i j k l m n 1 1 0 X 1 X 1 1 X X 1 1 X X

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