ASSIGNMENT 5 Design a 32-bit register file consisting of 32 registers with one r
ID: 3755630 • Letter: A
Question
ASSIGNMENT 5 Design a 32-bit register file consisting of 32 registers with one read port and one write port High Level Block Diagram of Register File showing inputs and outputs: Write Enable Register File Register Array RO R1 R2 R3 14:01 Address Write R4 R5 R6 R7 31:01 White Data R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R3 14:0) Read 4.0] Address 31.0] Read Data CLK A register file is just a collection of registers in one location. This is often seen inside various CPU's for fast, temporary storage of information. A register file can actually be created in Verilog within just one Verilog module. The heart of the register file is its array of registers, in Verilog we can define a register as: reg 17:0] example; This creates one register named "example" with a size of 8-bits. All we have to do to make an array of registers is to simply define in Verilog: reg 17:0] example2 [31:0 What this does is it creates 32 registers with the size of each register as 8-bits. After declaration of the above register array, one can access contents of an individual register by stating: example215'bo0000]8'h4F; This example puts the 32-bit hex value "4F" into example2's first register in the array (the 0'th register).Explanation / Answer
//######################## DESIGN CODE #################################
// Code your design here
module register_file(input clk, WriteE,[7:0] WriteD,[4:0] ReadA,[4:0] WriteA,output reg [7:0]ReadD);
reg [7:0] Array [31:0];
assign ReadD = (!WriteE)?Array[ReadA]:32'bz;//asynchronous read
always @(posedge clk)
begin
if(WriteE)
begin
Array[WriteA] <=WriteD;//synchronous write
end
end
initial begin
$monitor($time," ns WriteE=%0b, WriteD=%0h, ReadA=%0h, WriteA=%0h, ReadD=%0h Array[WriteA]=%0p Array[ReadA]=%0p ",WriteE, WriteD,ReadA, WriteA,ReadD,Array[WriteA],Array[ReadA]);
#50 $finish;
end
endmodule
############################ TESTBENCH CODE ##########################
// Code your testbench here
// or browse Examples
module tb;
reg clk, WriteE;
reg[31:0] WriteD;
reg[4:0] ReadA,WriteA;
wire [31:0] ReadD;
register_file uut(clk, WriteE, WriteD,ReadA, WriteA,ReadD);
initial begin
clk=0;
WriteE=0;
WriteD=0;
ReadA=0;
WriteA=0;
end
always #5 clk=!clk;
initial begin
// Write operation
@(posedge clk) begin
WriteE=1;
WriteD=8'h8F;
WriteA=5'b00000;
end
//Write opeartion
@(posedge clk) begin
WriteE=1;
WriteD=8'h35;
WriteA=5'b01010;
end
//Read operation
#2 begin // asynchronous read
WriteE=0;
ReadA=5'b00000;
end
end
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule
##################### CODE LINK- https://www.edaplayground.com/x/4wVC
###################
that argument inside [ ] of example2 represents Write Address. that statement says writing the value 8'h4F at location 5'b00000 i.e at 0 address.
**NOTE :-8'h4F is 8 bit hexadecimal value and not 32 bit as mentioned in question.
**NOTE:- In your code data at each location should be 8 bit wide as array declaration is [7:0]Array[can be any depth] for example in this question depth is 32.
Therefore read data(ReadD) and write data(WriteD) should be 8 bit wide and not 32 bit whch is wrongly mentioned in your code.
** CORRECT - reg[7:0]ReadD .