Please show the steps of the answer, Thanks Question is rom the book: Computer O
ID: 3765396 • Letter: P
Question
Please show the steps of the answer, Thanks Question is rom the book: Computer Organization and Architecture Designing for Performing, Ninth Edition
14.10 A nonpipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 G a. What is the speedup achieved for a typical program? b. What is the MIPS rate for each processor? HzExplanation / Answer
The machine takes 4 cycles / 2.5 GHZ = 1.6 nsec/instruction
The 5 staged pipeline processor has a clock rate of 2 GHz and an average CPI of 4.
This machine would take:
4 cycles / 2 GHz = 4 nsec/instruction if it were not pipelined.
Being a 5 stage pipelined machine, it has a speed up of up to 5, or takes:
2 nsec/instruct / 5 = .4 nsec/instruct.
It therefore has a speed up of 1.6 / .4 = 4 over the unpipelined machine.
With pipelining, each instruction needs, old execution time * old frequency/new frequency (without pipelining) = 1.6 * 2.5 / 2 = 2 ns