Question
Consider the instruction "CMP RA, 3Fh" (assume RA = 22h, RB = 21 h, RC=37h, RD=52h). Assume we are shortly before the clock edge of the "execute" cycle (i.e. at the next rising edge the instruction will be executed). By analyzing the VHDL code of the processor, explain what happens inside the educational processor to execute this instruction. Specifically, indicate the state of the following signals (or indicate if undefined): instruction (in cpu.vhd) rrd1 (port of cpuregbank in cpu.vhd) rrd2 (port of cpuregbank in cpu.vhd) rwr (port of cpuregbank in cpu.vhd) d (port of cpuregbank in cpu.vhd) reg2out (in cpu.vhd) reg2out (in cpu.vhd) source (in cpu.vhd) regwren (in cpu.vhd) flagwren (in cpu.vhd) ram we (in cpu.vhd) ram address (in cpu.vhd) ram_datawr (in cpu.vhd) op (port of cpualu in cpu.vhd) a (port of cpualu in cpu.vhd) b (port of cpualu in cpu.vhd)
Explanation / Answer
entity program_counter is port ( clk, en_A, ld, inc, reset: in STD_LOGIC; aBus: out STD_LOGIC_VECTOR(15 downto 0); dBus: in STD_LOGIC_VECTOR(15 downto 0) ); end program_counter; architecture pcArch of program_counter is signal pcReg: STD_LOGIC_VECTOR(15 downto 0); begin process(clk) begin if clk'event and clk = '1' then if reset = '1' then pcReg