This problem is for VHDL language implemented on FPGA implementing a design that
ID: 3778201 • Letter: T
Question
This problem is for VHDL language implemented on FPGA
implementing a design that will display the number of days in a month. The circuit will begin by displaying the number of days in January and cycle through a display of the number of days in the 11 remaining months. This 12 month cycle will then repeat until disabled. This design will have a minimum of two inputs (leap year, start/stop) and be able to display the number of days in the month as well as indicate the current month. One additional user selectable feature should also be implemented.
Explanation / Answer
with your assignment. It accepts the binary value of month, 1-12, and if it is a leap year or not, and outputs the number of days in that month. This is done without a clock (combinatorial/asynchronous logic).
I think you can take this and determine the best way to use sequential statements to create an alternative implementation based on what you assignment is asking for.