Assuming it takes 10 clock cycles to access cache and 1000 cycles to access (D)R
ID: 3783729 • Letter: A
Question
Assuming it takes 10 clock cycles to access cache and 1000 cycles to access (D)RAM, how many cycles would the sequence of accesses in Ex. 5.2.2 take using the same cache configuration as 5.2.2 (8 two-word blocks) if every other one was a write (i.e. READ 3, WRITE 180, READ 43, WRITE 2, etc.) on the following types of caches:
a. Write-Through
b. Write-Back
Information for 5.2.2 provided below:
Given the addresses:
3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253
5.2.2 For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
Answer:
Address - Binary- Tag- Index- Hit/Miss
3 00000011 0000 001 Miss
180 10110100 1011 010 Miss
43 00101011 0010 101 Miss
2 00000010 0000 001 Hit
191 10111111 1011 111 Miss
88 01011000 0101 100 Miss
190 10111110 1011 111 Hit
14 00001110 0000 111 Miss
181 10110101 1011 010 Hit
44 00101100 0010 110 Miss
186 10111010 1011 101 Miss
253 11111101 1111 110 Miss
Explanation / Answer
The index should be left shifted one bit
write-back cache which requires a block to be replaced
often require two memory accesses to service:
one to write the replaced data from the
write-through cache uses no-write allocate.