An inhibited toggle flip-flop has inputs 10, I1, T, and Reset, and outputs Q and
ID: 3786501 • Letter: A
Question
An inhibited toggle flip-flop has inputs 10, I1, T, and Reset, and outputs Q and QN Reset is active high and overrides the action of the other inputs. I Tie flip-flop work, as follows. If I0 = '1', the flip-flop changes state on the rising edge of T: if I1 = '1'. the flip-flop changes stale on the falling edge of T. If I0 = I1 = '0', no state change occurs (except on reset). Assume the propagation delay from T to output is 8 ns and from reset to output is 5 ns. (a) Write a complete VHDL description of this flip-flop. (b) Write a sequence of simulator commands that I1 = '1', toggle T twice, I1 = '0', I0 = '1', toggle T twice.Explanation / Answer
a)
The verilog code for the inhibited toggle flip-f;op is as follow:
module inhibitedToggleFlipFlop)I0,I1,Reset,Q,QN);
Input I0,I1,T,Reset;
output Q,QN;
reg Q,QN;
Initial
begin
Q=0;
QN=1;
end
always @(I0 or I1 or Reset)
begin
if (Reset) begin
//if Reset is set then initialize to 0 and QN to 1 with a delay of 5ns
Q<#5a'b0;
QN<=#51'b1;
end
else id(I0!=I1) begin
// The flip-flop works on the both positive as well as negatice edge T when I0 is not equal to I1 with a delay of 8ns
if(I0==1'b1)begin
Q<=#8!Q;
QN<=#8!QN;
end
else if(I1==1'b1 and posedge T) begin
Q<=#8!Q;
QN<=#8!QN;
end
end
else if (I0==I1 and nededge T) begin
q<=Q;
Qn<=QN;
end
end
endmodule
The code is he described code for the inhibited toggle flip flop responds to dalling edge of T as well as raising edge of T.