Part a) The instruction (BEQ R1, R2, Label) is at address 1200 and branches to a
ID: 3787092 • Letter: P
Question
Part a) The instruction (BEQ R1, R2, Label) is at address 1200 and branches to address 1600. Show the encoding of the instruction using the direct addressing mode.
Part b) Repeat the above using the PC-relative addressing mode.
Part c) What is the benefit of the PC-relative addressing mode?
Part d) List three approaches that an architecture could use for saving (linking) the return address when a subroutine is called.
Part e) An architecture is being upgraded from 32-bit to 64-bit. It will have 64-bit registers and a 64-bit ALU. Does it make sense to make the immediate fields 40-bit?
Explanation / Answer
a)
BEQ is a jumping instruction. If R1 and R2 are equal, then the result will be in label.
R1 has address 1200
R2 has branch address 1600
BEQ = 0x4
R1 = 0x9
R2 = 0Xa
The value of label will be as follows:
label = 0x640
The encoding instruction format is as follows:
Opcode (6 bits)
R1(base) (5 bits)
R2(destination) (5bits)
Address offset
The opcode for this format is 000100 which is 6 bit.
R1(source/base register) = 0x9 = 01001 which is 5 bit.
R2(destination register) = 0XA = 01010 which is 5 bit in length.
Label = 640 = 0000 0110 0100 0000
The instruction format is as follows:
000100
01001
01010
0000011001000000
b)
Using the PC-relative addressing mode the operand address will be as follows:
PC + offset
A small offset can adequate for the short loops.
The instruction which is given is: BEQ (R1, R2, label)
For the better understanding take an example as follows:
BEQ ($0, $3, label)
The instruction format is as follows:
Opcode (5 bits)
Source (5 bits)
Destination (5 bits)
Immediate value
The number of bits allocated for each of the following: opcode, source, destination and the immediate value(label) are as follows:
Opcode = 00010
Source = 00000
Destination = 00101
label = 0000000000000010
The format is as follows:
000100
00000
00101
0000000000000010
c)
The benefit of PC-relative addressing mode is that it is used to load a register that has the value which is very close to the current instruction and this value is stored in memory.
PC is a special purpose register that contains the address of the next instruction that is to be fetched.
d)
The 3 approaches that an architecture could use for saving the return address when a subroutine is called are as follows:
e)
An architecture is being upgraded from 32 bit to 64 bit. It will have 64 bit registers and a 64 bit ALU. It does not make sense to make the immediate fields 40 bit because 40 bit is not enough while 64 bit is a large number having large power of 2.
Opcode (6 bits)
R1(base) (5 bits)
R2(destination) (5bits)
Address offset