Consider a system with a byte-addressable virtual address space of 65536 bytes,
ID: 3793779 • Letter: C
Question
Consider a system with a byte-addressable virtual address space of 65536
bytes, and a physical address space of 64 32-bit words.
a. Assume that said system has an 8 entry cache with a block size of 8
bytes and an associativity of 1. Further assume that the cache is both
virtually indexed and virtually tagged. If the cache entries are all
initially invalid, what is the state of the cache (given as a table
indicating the <valid, tag, MEM(x)> tuple for each cache set) after
reads have been issued for word addresses 8, 6, 7, 5, 3, 0, 9?
b. What is the state of the cache if block size and capacity are held
constant, but associativity increases to 2 with LRU replacement?
c. What is the state of the cache if block size and capacity are held
constant, associativity increases to 2 with LRU replacement, and the
cache is virtually indexed and physically tagged, assuming that there
are 1KB pages and that the first 2 virtual pages (0 and 1) are mapped
into the first two physical pages?
ONLY ANSWER PART B PLEASE
Explanation / Answer
Block 12 placed in 8 block cache: – Fully associative, direct mapped, 2- way set associative – S.A. Mapping = Block Number Modulo Number Sets (associativity = degree of freedom in placing a particular block of memory) (set = a collection of blocks cache blocks with the same cache index)
Direct Mapped is Easy Set associative or fully associative: – “Random” (large associativities) – LRU (smaller associativities) – Pseudo Associative Associativity: 2-way 4-way 8-way Size LRU Random LRU Random LRU Random 16 KB 5.18% 5.69% 4.67% 5.29% 4.39% 4.96% 64 KB 1.88% 2.01% 1.54% 1.66% 1.39% 1.53% 256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12% Numbers are averages across a set of benchmarks. Performance improvements vary greatly by individual benchmarks.
CPU time = (CPU execution clock cycles + Memory stall clock cycles) x clock cycle time Memory stall clock cycles = (Reads x Read miss rate x Read miss penalty + Writes x Write miss rate x Write miss penalty) Memory stall clock cycles = Memory accesses x Miss rate x Miss penalty