Question
Need help with VHDL code.
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned valuesuse IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating-- any Xilinx leaf cells in this code.--library UNISIM;--use UNISIM.VComponents.all;
entity task1_tb is-- Port ( );end task1_tb;
architecture Behavioral of task1_tb is
--declaring the componentcomponent task1 Port ( a : in STD_LOGIC; b : in STD_LOGIC; y : out STD_LOGIC);end component;
--declaring the signals needed--these y,a,b signals are different from the--internal ones of the componentsignal y,a,b: std_logic;
--signal to assign values to a and bsignal counter: unsigned(1 downto 0):="00";
begin
-- component assignmentuut: task1 port map(a => a,b => b,
y => y
);
--assign a (bit 1) and b (bit 0) to the counter bits so that--all possible inputs are tested
--Enter your code here
--increments the counter using a process--use a 20ns delay between each combination
--Enter your code here
--assign operation results to y
--Enter your code here
end Behavioral;
Explanation / Answer
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity newmult is Port ( clk : in STD_LOGIC; rst : in std_logic; trig : in std_logic; in0M : in STD_LOGIC_VECTOR (30 downto 0); in1M : in STD_LOGIC_VECTOR (30 downto 0); outputM : out STD_LOGIC_VECTOR (30 downto 0)); end newmult; architecture Behavioral of newmult is component DSP48E generic ( ACASCREG : integer := 1; ALUMODEREG : integer := 1; AREG : integer := 1; AUTORESET_PATTERN_DETECT : boolean := FALSE; AUTORESET_PATTERN_DETECT_OPTINV : string := "MATCH"; A_INPUT : string := "DIRECT"; BCASCREG : integer := 1; BREG : integer := 1; B_INPUT : string := "DIRECT"; CARRYINREG : integer := 1; CARRYINSELREG : integer := 1; CREG : integer := 1; MASK : bit_vector := X"3FFFFFFFFFFF"; MREG : integer := 1; MULTCARRYINREG : integer := 1; OPMODEREG : integer := 1; PATTERN : bit_vector := X"000000000000"; PREG : integer := 1; SEL_MASK : string := "MASK"; SEL_PATTERN : string := "PATTERN"; SEL_ROUNDING_MASK : string := "SEL_MASK"; USE_MULT : string := "MULT"; USE_PATTERN_DETECT : string := "NO_PATDET"; USE_SIMD : string := "ONE48"); port ( ACOUT : out std_logic_vector(29 downto 0); BCOUT : out std_logic_vector(17 downto 0); CARRYCASCOUT : out std_logic; CARRYOUT : out std_logic_vector(3 downto 0); MULTSIGNOUT : out std_logic; OVERFLOW : out std_logic; P : out std_logic_vector(47 downto 0); PATTERNBDETECT : out std_logic; PATTERNDETECT : out std_logic; PCOUT : out std_logic_vector(47 downto 0); UNDERFLOW : out std_logic; A : in std_logic_vector(29 downto 0); ACIN : in std_logic_vector(29 downto 0); ALUMODE : in std_logic_vector(3 downto 0); B : in std_logic_vector(17 downto 0); BCIN : in std_logic_vector(17 downto 0); C : in std_logic_vector(47 downto 0); CARRYCASCIN : in std_logic; CARRYIN : in std_logic; CARRYINSEL : in std_logic_vector(2 downto 0); CEA1 : in std_logic; CEA2 : in std_logic; CEALUMODE : in std_logic; CEB1 : in std_logic; CEB2 : in std_logic; CEC : in std_logic; CECARRYIN : in std_logic; CECTRL : in std_logic; CEM : in std_logic; CEMULTCARRYIN : in std_logic; CEP : in std_logic; CLK : in std_logic; MULTSIGNIN : in std_logic; OPMODE : in std_logic_vector(6 downto 0); PCIN : in std_logic_vector(47 downto 0); RSTA : in std_logic; RSTALLCARRYIN : in std_logic; RSTALUMODE : in std_logic; RSTB : in std_logic; RSTC : in std_logic; RSTCTRL : in std_logic; RSTM : in std_logic; RSTP : in std_logic ); end component; --Signal Declarations: SIGNAL PCOUT1, PCOUT2, PCOUT3, PCOUT4, PCOUT5 : std_logic_vector(47 DOWNTO 0); SIGNAL a1s, a2s : std_logic_vector(29 DOWNTO 0); SIGNAL b1s, b2s : std_logic_vector(17 DOWNTO 0); SIGNAL LOW_18bit : std_logic_vector(17 downto 0); SIGNAL LOW_30bit : std_logic_vector(29 downto 0); SIGNAL LOW_48bit : std_logic_vector(47 downto 0); SIGNAL LOW_1bit : std_logic; SIGNAL HIGH_1bit : std_logic; -- Architecture Section: instantiation block 1 BEGIN LOW_18bit "MATCH", A_INPUT => "DIRECT", BCASCREG => 1, BREG => 1, B_INPUT => "DIRECT", CARRYINREG => 0, CARRYINSELREG => 1, CREG => 1, MASK => X"3FFFFFFFFFFF", MREG => 1, MULTCARRYINREG => 0, OPMODEREG => 0, PATTERN => X"000000000000", PREG => 1, SEL_MASK => "MASK", SEL_PATTERN => "PATTERN", SEL_ROUNDING_MASK => "SEL_MASK", USE_MULT => "MULT_S", USE_PATTERN_DETECT => "NO_PATDET", USE_SIMD => "ONE48") port map ( ACOUT => open, BCOUT => open, CARRYCASCOUT => open, CARRYOUT => open, MULTSIGNOUT => open, OVERFLOW => open, P => PCOUT1, PATTERNBDETECT => open, PATTERNDETECT => open, PCOUT => open, UNDERFLOW => open, A => a2s, ACIN => LOW_30bit, ALUMODE => "0000", B => b2s, BCIN => LOW_18bit, C => LOW_48bit, CARRYCASCIN => '0', CARRYIN => '0', CARRYINSEL => "000", CEA1 => '0', CEA2 => '1', CEALUMODE => '1', CEB1 => '0', CEB2 => '1', CEC => '1', CECARRYIN => '0', CECTRL => '1', CEM => '0', CEMULTCARRYIN => '0', CEP => '1', CLK => clk, MULTSIGNIN => '0', OPMODE => "0000101", PCIN => LOW_48bit, RSTA => rst, RSTALLCARRYIN => rst, RSTALUMODE => rst, RSTB => rst, RSTC => rst, RSTCTRL => rst, RSTM => rst, RSTP => rst ); mult: process(clk) begin if(clk'event and clk = '1' and trig = '1') then a1s