I have the solution, but can anyone explain to me how to reach the final output?
ID: 3804475 • Letter: I
Question
I have the solution, but can anyone explain to me how to reach the final output? A diagram would be nice.
Given the following implementation of a gated(clocked) S-R latch
fill in its truth table:
E
Q(t)
S(t)
R(t)
Q(t+1)
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
?
1
1
0
0
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
?
use “?” for undefined states (i.e., when ).
Q(t), S(t), R(t) are the values of Q, S and R at time t, while Q(t+1) is the value of Q at time t+1 (after applying new inputs).
E
Q(t)
S(t)
R(t)
Q(t+1)
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
?
1
1
0
0
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
?
[O SExplanation / Answer
When the Enable signal is OFF, there is no change from the current state to next state, therefore, Q(t+1) will be the same as Q(t) for what ever the S, and R values are.
Simply speaking in an SR latch, the S stands for Set, and R stands for Reset.
So, when Set and Reset both are 0, then there will be no change for the next state.
When Set is 1, and Reset is 0, the next state will be set(1) irrespective of the previous state.
When Set is 0, and Reset is 1, the next state will be reset(0) irrespective of the previous state.
When both Set and Reset are 1, that leads to an invalid state.
E
Q(t)
S(t)
R(t)
Q(t+1)
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
?
1
1
0
0
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
?
E
Q(t)
S(t)
R(t)
Q(t+1)
Description.0
0
0
0
0
Q(t+1) is same as Q(t)0
0
0
1
0
Q(t+1) is same as Q(t)0
0
1
0
0
Q(t+1) is same as Q(t)0
0
1
1
0
Q(t+1) is same as Q(t)0
1
0
0
1
Q(t+1) is same as Q(t)0
1
0
1
1
Q(t+1) is same as Q(t)0
1
1
0
1
Q(t+1) is same as Q(t)0
1
1
1
1
Q(t+1) is same as Q(t)1
0
0
0
0
Here, the next state will be same as previous state.1
0
0
1
0
Here the next state is RESET(0)1
0
1
0
1
Here the next state is SET(1)1
0
1
1
?
This leads to an invalid state.1
1
0
0
1
Here, the next state is same as previous state.1
1
0
1
0
Here the next state is RESET(0)1
1
1
0
1
Here the next state is SET(1)1
1
1
1
?
This leads to an invalid state.