The following Verilog code is behavioral model of 4-to-1-line multiplexer and th
ID: 3814503 • Letter: T
Question
The following Verilog code is behavioral model of 4-to-1-line multiplexer and the stimulus. Fill in the space with underline.
//Design module of 4-to-1-line MUX
module mux4_1_bh (__ I, ____select, ____y);
//I is data input, select is selection lines, y is output
reg y; //y is of data type reg
always @ (____or____)
case (select)
2’b00: y = I[0];
2’b01: y =_____;
2’b10: y =I[2];
____________;
endcase
endmodule
//stimulus
module test_mux ;
_____ [3: 0] D;
_____ [1:0] S;
_____ Y;
//instantiate mux4_1_bh
______________________________; //follow Verilog-2001 standard
//start simulation, provide stimulus to the module under test
initial
begin
D = 4’b0101;
S = 2’b00;
repeat (3)
_________________________; //increase S by 1
end
initial
//monitor D, S, Y
$monitor (_________________________________________________);
endmodule
Explanation / Answer
//Design module of 4-to-1-line MUX
module mux4_1_bh (__input [3:0] I, input [1:0]____select, output____y);
//I is data input, select is selection lines, y is output
reg y; //y is of data type reg
always @ (I____or_select___)
case (select)
2’b00: y = I[0];
2’b01: y = I[1]____;
2’b10: y =I[2];
2'b11: y =I[3];____________;
endcase
endmodule
//stimulus
module test_mux ;
_input____ [3: 0] D;
_input __ [1:0] S;
_output____ Y;
//instantiate mux4_1_bh
mux4_1_bh (.I(D),.select(S),.y(Y))_____________________________; //follow Verilog-2001 standard
//start simulation, provide stimulus to the module under test
initial
begin
D = 4’b0101;
S = 2’b00;
repeat (3) begin
if (S == 2'b11)
S = 2'b00;
else
S = S + 1;
end
_______________________; //increase S by 1
end
initial begin
//monitor D, S, Y
$monitor (%g D = %4b,S = %2b,Y= %b",$time,D,S,Y);
end _________________________________________________);
endmodule
Please let me know in case of any doubts.
Thanks