Assume that individual stages of the data path have the following latencies :- I
ID: 3832487 • Letter: A
Question
Assume that individual stages of the data path have the following latencies :-
IF
ID
EX
MEM
WB
150ps
150ps
120ps
130ps
140ps
a. What is the clock cycle time in a pipelined and a single cycle non-pipelined processor?
b. What is the latency of an instruction in a pipelined and a single cycle non-pipelined processor?
c. What are the speed-up that could be achieved with the pipelined processor over the non- pipelined processor for two programs containing 10 instructions and 10000 instructions, respectively?
IF
ID
EX
MEM
WB
150ps
150ps
120ps
130ps
140ps
Explanation / Answer
a)Time for 1 instruction in pipeline = 150ps = max(150, 150, 120, 130, 140)
Clock cycle time in pipelined = 6.67 GHz
Time for 1 instruction in non-pipeline = 690ps = add(150, 150, 120, 130, 140)
Clock cycle time in Non- pipelined = 1.449 GHz
b) latency of an instruction in a pipelined = 150*5 = 750ps
latency of an instruction in a non-pipelined = 690ps
c) Time Require to execute 10 instructions:
Pipeline = 14*150 = 2100ps
Non-Pipeline = 690*10 = 6900 ps
SpeedUp = 6900/2100 = 3.2857
Time Require to execute 100 instructions:
Pipeline = 104*150 = 15600ps
Non-Pipeline = 690*100 = 69000 ps
SpeedUp = 69000/15600 = 4.423