Create a 3 pages research paper that investigates the of the properties of the 8
ID: 3840879 • Letter: C
Question
Create a 3 pages research paper that investigates the of the properties of the 80- 86 Intel processor The paper must include the following sections: i. Introduction 0.5 page ii. Actual architecture 1 page iii. The purpose of each register 1 page iv. Conclusion 0.5 page v. Annotated Bibliography The introduction should be no more than a half page long and should clearly state the objective of your paper. It should also provide a brief history of C The architecture section should explain to the la how a cPu works. It should include all the registers and flags and how are they being used by the computer The conclusion should relate to the objective(s) stated in the introduction and summarizes the highlights of the paper. The annotated bibliography must conform to MLA format standards. All your sources must have references. Pay attention to the content, grammar and style.Explanation / Answer
Introduction:
In this introduction part I will give a brief description of how, when and why 8086 processor came into existence.
Development of the 8086 processor project started in 1976 .It was an attempt to draw attention from the less-delayed 16- and 32-bit processors of other manufacturers and and at the same time to counter the threat from the Zilog Z80. The 8086 was designed to allow assembly language for the 8008, 8080, or 8085 to be automatically converted into equivalent 8086 source code.
The 8086 has complete 16-bit architecture - 16-bit internal registers, 16-bit data bus, and 20-bit address busThe segments can be positioned anywhere in memory, and, if necessary, user programs can change their position. This addressing method has one big advantage - it is very easy to write memory-independent code when the size of code, stack and data is smaller than 64 KB each. The complexity of the code and programming increases, sometimes significantly, when the size of stack, data and/code is larger than 64 KB.
ARCHITECTURE:
The 8086 CPU is divided into two independent functional parts, the Bus interface unit (BIU) and execution unit (EU).
The Bus Interface Unit contains Bus Interface Logic, Segment registers, Memory addressing logic and a Six byte instruction object code queue. The BIU sends out address, fetches the instructions from memory, read data from ports and memory, and writes the data to ports and memory.
The execution unit: contains the Data and Address registers, the Arithmetic and Logic Unit, the Control Unit and flags. tells the BIU where to fetch instructions or data from, decodes instructions and executes instruction. The EU contains control circuitry which directs internal operations. A decoder in the EU translates instructions fetched from memory into a series of actions which the EU carries out. The EU is has a 16-bit ALU which can add, subtract, AND, OR, XOR, increment, decrement, complement or shift binary numbers. The EU is decoding an instruction or executing an instruction which does not require use of the buses.In other words the BIU handles all transfers of data and addresses on the buses for the execution unit.
The Queue: The BIU fetches up to 6 instruction bytes for the following instructions. The BIU stores these prefetched bytes in first-in-first-out register set called a queue. When the EU is ready for its next instruction it simply reads the instruction byte(s) for the instruction from the queue in the BIU. This is much faster than sending out an address to the system memory and waiting for memory to send back the next instruction byte or bytes.
Registers in 8086:
General-Purpose registers:
AX: Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations, rotate and string manipulation.
BX: Base register holds the starting base location of a memory region within a data segment. It is used as offset storage for forming physical address in case of certain addressing mode.
CX: count register in case of string and loop instructions.
DX: Data register can be used as a port number in I/O operations and implicit operand or destination in case of few instructions. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.
Segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. It is used for addressing stack segment of memory. The stack segment is that segment of memory, which is used to store stack data.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. It points to the data segment memory where the data is resided.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It also refers to segment which essentially is another data segment of the memory.
Pointers and index registers.
Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.
Flag Register:
Flags Register determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program.
Conditional Flags:
Carry Flag (CY): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic.
Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a general-purpose flag, it is used internally by the Processor to perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set.
Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit. Control flags are as follows:
Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction sit and can be cleared by executing CLI instruction.
Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower memory address. When it is reset, the string bytes are accessed from lower memory address to higher memory address.