Consider an Intel 80386DX-based system using a 32-bit external data bus. a. Comp
ID: 3852530 • Letter: C
Question
Consider an Intel 80386DX-based system using a 32-bit external data bus. a. Complete the memory structure 9below) using the 4 banks. Clearly denote the bank enable signals that are used to enable each bank. Use bus notation for the address and data bus lines going to each bank. Please note that, instead of using A0 and A1, the proper notation for the bank enable signals is BE_0, BE)1, BE_2, and BE_3, (all active low, and controlled by the 80386). Lastly, clearly note which data lines go to which memory banks. b. Which bank enable lines would be enabled for... b. A byte from an address that is divisible by 4? c. a word that starts at an address that is divisible by 2, but not 4? (show some examples to figure this out!) c. a double word that starts at an odd address? Two accesses would be required - why?Explanation / Answer
Answer for the Question:
As given data banks in the problem statement .
A byte address is divisible 4 means i.e
0%4 = 0
1%4 = 1
2%4 = 2
3%4 = 3
As if you looked into above operations . A address can be divisible by 4 can
have access to store any of the given data banks
A word address is divisible by 2 but not 4
in this case number divisible by 2 means either 0 or 1
in that case only Ban 0 or Bank 1 is access
word that starts on an odd address but does not cross a word
boundary is considered aligned and can still be accessed in one bus cycle