Pattern generator- verilog code This must be coded in verilog In this assignment
ID: 3853491 • Letter: P
Question
Pattern generator- verilog code
This must be coded in verilog
In this assignment we will program a sequential circuit in Verilog code as a pattern generator which generates, instead of binary counts, your Firstname (space) Lastname (space), character by character. Display the pattern sequence for at least two cycles (run the demo).
Suppose the output of the ripple sequencer is an arrray of q. Then, the truth table of encoding is:
Below is the code, the CoderMod module is the only one that needs to be completed. The size of the arrays in the other 2 modules might need to be adjusted. Please use "First [space] Lastname" for the name in the ascii code.
--------------------------------------------------------------------
module TestMod;
reg CLK;
wire [0:11] Q;
wire [6:0] ascii;
initial begin
#1;
forever begin
CLK=0;
#1;
CLK=1;
#1;
end
end
RippleMod my_ripple(CLK, Q);
CoderMod my_coder(Q, ascii);
initial #27 $finish;
initial begin
$display("Time CLK Q Name");
$monitor("%4d %b %b %c %x %b", $time, CLK, Q, ascii, ascii, ascii);
end
endmodule
module CoderMod(Q, ascii);
...
endmodule
module RippleMod(CLK, Q);
input CLK;
output [0:15]Q;
reg [0:15]Q;
always @(posedge CLK) begin
Q[0] <= Q[15];
Q[1] <= Q[0];
Q[2] <= Q[1];
Q[3] <= Q[2];
Q[4] <= Q[3];
Q[5] <= Q[4];
Q[6] <= Q[5];
Q[7] <= Q[6];
Q[8] <= Q[7];
Q[9] <= Q[8];
Q[10] <= Q[9];
Q[11] <= Q[10];
Q[12] <= Q[11];
Q[13] <= Q[12];
Q[14] <= Q[13];
Q[15] <= Q[14];
end
initial begin
Q[0] = 1;
Q[1] = 0;
Q[2] = 0;
Q[3] = 0;
Q[4] = 0;
Q[5] = 0;
Q[6] = 0;
Q[7] = 0;
Q[8] = 0;
Q[9] = 0;
Q[10] = 0;
Q[11] = 0;
Q[12] = 0;
Q[13] = 0;
Q[14] = 0;
Q[15] = 0;
end
endmodule
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Thanks!
Link to assignment if needed: http://athena.ecs.csus.edu/~changw/137/prg/5PatternGenerator/
Pattern Generator Ripple Sequence Generator 5 7 (ASCII) Pattern Encoder CLK Ripple Sequence Generator CLKExplanation / Answer
You have few issues in your code... you declared ascii arrays as wire [6:0] ascii; but you are trying to connect to module as CodeMod my_coder(Q,ascii); where it has output port of width 14. So you need to declare..
wire [6:0] ascii [13:0];
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module TestMod;
reg CLK;
wire [0:11] Q;
wire [6:0] ascii [13:0];
initial begin
#1;
forever begin
CLK=0;
#1;
CLK=1;
#1;
end
end
RippleMod my_ripple(CLK, Q);
CoderMod my_coder(Q, ascii);
initial #27 $finish;
initial begin
$display("Time CLK Q Name");
$monitor("%4d %b %b %c %x %b", $time, CLK, Q, ascii, ascii, ascii);
end
endmodule
module CoderMod(Q, ascii);
input [0:13]Q;
output [13:0] ascii;
assign ascii[0] = "F";
assign ascii[1] = "i";
assign ascii[2] = "r";
assign ascii[3] = "s";
assign ascii[4] = "t";
assign ascii[5] = " ";
assign ascii[6] = "L";
assign ascii[7] = "a";
assign ascii[8] = "s";
assign ascii[9] = "t";
assign ascii[10] = "n";
assign ascii[11] = "a";
assign ascii[12] = "m";
assign ascii[13] = "e";
or(ascii[0], Q[13]);
or(ascii[1], Q[12]);
or(ascii[2], Q[11]);
or(ascii[3], Q[10]);
or(ascii[4], Q[9]);
or(ascii[5], Q[8]);
or(ascii[6], Q[7]);
or(ascii[7], Q[6]);
or(ascii[8], Q[5]);
or(ascii[9], Q[4]);
or(ascii[10], Q[3]);
or(ascii[11], Q[2]);
or(ascii[12], Q[1]);
or(ascii[13], Q[0]);
endmodule
module RippleMod(CLK, Q);
input CLK;
output [0:15]Q;
reg [0:15]Q;
always @(posedge CLK) begin
Q[0] <= Q[15];
Q[1] <= Q[0];
Q[2] <= Q[1];
Q[3] <= Q[2];
Q[4] <= Q[3];
Q[5] <= Q[4];
Q[6] <= Q[5];
Q[7] <= Q[6];
Q[8] <= Q[7];
Q[9] <= Q[8];
Q[10] <= Q[9];
Q[11] <= Q[10];
Q[12] <= Q[11];
Q[13] <= Q[12];
Q[14] <= Q[13];
Q[15] <= Q[14];
end
initial begin
Q[0] = 1;
Q[1] = 0;
Q[2] = 0;
Q[3] = 0;
Q[4] = 0;
Q[5] = 0;
Q[6] = 0;
Q[7] = 0;
Q[8] = 0;
Q[9] = 0;
Q[10] = 0;
Q[11] = 0;
Q[12] = 0;
Q[13] = 0;
Q[14] = 0;
Q[15] = 0;
end
endmodule