Consider the following sequence of instructions. lw $t1, 4($t2) lw $t2, 4($t1) a
ID: 3870063 • Letter: C
Question
Consider the following sequence of instructions.
lw $t1, 4($t2)
lw $t2, 4($t1)
add $t3, $t1, $t2
sw $t3, 8($t1)
lw $t4, 12($t0)
add $t5, $t1, $t4
sw $t5, 16($t2)
Assume that the pipeline has full forwarding support.
1.Without reordering the instructions, insert nops to ensure correct execution
2.To minimise the number of nops, how would you reorder the instructions without changing the outcome of the execution?
3.For the last three instructions (copied below), give the conditions (discussed in the class) for detecting the hazards (you need specify the register number, using the register number provided in the instructions instead of Register Rs/Rt/Rd).
lw $t4, 12($t0)
add $t5, $t1, $t4
sw$t5,16($t2)
Explanation / Answer
nop is used to delay the next instruction, if it has data hazard with current instruction.
1. Following is the program after inserting nop, which is happening due to Read After Write(RAW) hazard with next instruction.
lw $t1, 4($t2)
nop #because of Read After Write(RAW) hazard with next instruction
lw $t2, 4($t1)
nop #because of Read After Write(RAW) hazard with next instruction
add $t3, $t1, $t2
nop #because of Read After Write(RAW) hazard with next instruction
sw $t3, 8($t1)
lw $t4, 12($t0)
nop #because of Read After Write(RAW) hazard with next instruction
add $t5, $t1, $t4
nop #because of Read After Write(RAW) hazard with next instruction
sw $t5, 16($t2)
2. Following is the reordering minimizing the number of nop to 1. Here we are reordering the instructions in such a way that previous instruction does not have any of Read After Write(RAW), Write After Read(WAR) and Write After Write(WAW) with next instruction. Also it does not change the output.
lw $t1, 4($t2)
lw $t4, 12($t0)
lw $t2, 4($t1)
add $t5, $t1, $t4
add $t3, $t1, $t2
nop #nop is required because either way of reordering of next two instructions will produce data hazard either with register $t1 or with $t2#
sw $t3, 8($t1)
sw $t5, 16($t2)
3.
lw $t4, 12($t0)
add $t5, $t1, $t4
sw$ t5,16($t2)
In the above given three instrctions, second instruction have Read After Write data hazard with first instruction because in first instruction register $t4 is written, which is being read by second instructions. Similarly third instruction have Read After Write data hazard with second instruction because in second instruction register $t5 is written, which is being read by third instructions.