Need help with VHDL coding Pre-Laboratory: (30%) The block diagram shown below r
ID: 3873630 • Letter: N
Question
Need help with VHDL coding
Pre-Laboratory: (30%) The block diagram shown below represents a calculator. The calculator design has three inputs and one output. A and B are each 4-bit numbers that will be operated on according to the table below. OP is a 2-bit input that determines which operation is to be performed on A and B. R is the 8-bit result of the operation A(3 downto 0) B(3 downto 0) OP(1 downto 7 89 R(7 downto 0) 1 2 3 0) Operation A B OP 01 10 A/ B 1. Write the VHDL module (entity and architecture) for the calculator. Use a case statement. Include the following libraries: » use IEEE.STD LOGIC 1164.ALL use IEEE.NUMERIC_STD.ALL; » Use std logic vectors in the entity . Use signed numbers in the architecture Refer to section 5.7 in the textbook for recommendations 2. Compile the VHDLExplanation / Answer
The below VHDL code satisfies the given requirements as follows:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Calculator is --entity for defining the inputs and outputs
port (
A: in std_logic_vector(3 downto 0)
B: in std_logic_vector(3 downto 0)
OP: in std_logic_vector(1 downto 0)
R: out std_logic_vector(7 downto 0)
);
end Calculator;
architecture BehavioralCalc of Calculator is
begin
process (A,B)
BEGIN
case OP is --case statement is to create the calculator operation
when "00"=> R <= A + B;
when "01"=> R <=A - B;
when "10"=> R <=A * B;
when "11"=> R <=A / B;
end case;
end process;
end BehavioralCalc;