Please answer fully explaining part a (ii) and (iii) in particular and part (b)
ID: 3875698 • Letter: P
Question
Please answer fully explaining part a (ii) and (iii) in particular and part (b)
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Question 3 (a) Consider a hypothetical machine with a byte-addressable main memory of 1 Mbyte and a block size of 16 bytes. Assume that a direct mapped cache consisting of 64 lines is used with this machine. (i) How many bytes in total can be stored in the cache? What is the length of a memory address? (i) Describe how the memory address is divided into tag, line number and byte number, giving the number of bits for each. (ii) Into which lines would bytes with each of the following addresses be stored? 0001 0001 0001 1011 1100 1100 0011 0011 1100 0101 1101 0000 0001 1101 1000 1010 1010 1010 1010 0000 (iv) Suppose the byte with address 0001 1010 1100 0001 1000 is stored in the cache. What other bytes are stored along with it in the same cache line? (b) A set associative cache has a block size of 8 bytes, and has 2-line sets. The capacity of the cache is 32 Kbytes and main memory can store 8 Mbytes. Describe how a main memory address is divided into tag, set number and byte number, giving the number of bits for eachExplanation / Answer
(a) Direct Mapped Cache
Block size is 16 bytes - number of bits for the offset in the block = 4 bits
Number of lines is 64 - number of bits to select a line (Block identifier) is 6 bits
i) Total bytes in the cache = 64 * 16 = 1024 bytes
ii) Total number of bits in the address is 20 as the main maemory is 1MB
Number of bits for tag = 20 - (Block identifier bits + Block offset bits)
= 20 - (6+4)
= 20 - 10
= 10 bits
iii) (we need to leave 4 least significant bits and then look for another 6 least significant bits)
0001 0001 0001 1011 1100- In this block identifier bits are 01 1011 = line 27
1100 0011 0011 1100 0101- In this block identifier bits are 11 1100 = line 60
1101 0000 0001 1101 1000- In this block identifier bits are 01 1101 = line 29
1010 1010 1010 1010 0000- In this block identifier bits are 10 1010 = line 42
iv) 0001 1010 1100 0001 1000 - We can vary the last 4 bits.last 4 bits 0000 - 1111
these range of addresses will be stored in the same cache line.
(b) Set Associative cache
It is 2-line set means 2-way set associative
Block size 8 bytes - offset in the block - 3 bits
Cache capacity = 32 Kbytes
Number of lines = 32 * 1024/(8 * 2) = 2^15/2^4 = 2^11 (11 bits)
Main Memory is 8 MBytes = 2^23 (23 bits)
Total address bits = 23
Tag bits = 23 - (Bits for lines(Set bits) + Block offset byte)
= 23 - (11 + 3)
= 23 - 14
= 9 bits