Consider two different implementations of the same instruction set architecture
ID: 3882976 • Letter: C
Question
Consider two different implementations of the same instruction set architecture (ISA). The instructions in each ISA can be divided into four classes according to their CPI (Class A,B,C,D). P1 has a clock rate of 2.5 GHZ and CPIs of 1,2,3,3 and P2 has a clock rate of 3 GHz and CPIs of 2,2,2,2.
a. Given a program with an instruction count of 1.0E6 instructions, where the instructions can be divided into classes as follows: 10 percent class A, 20 percent class B, 50 percent class C, and 20 percent class D, which is the fastest implementation?
b. What is the effective CPI for each implementation?
c. What is the required number of clock cycles to execute the program for each implementation?
Explanation / Answer
Gievn that there are two processors P1 and P2.
Instruction count = 106
Instructions are devides as four classes and as 10 percent class A, 20 percent class B, 50 percent class C, and 20 percent class D.
CPIs of P1 are: 1,2,3,3
CPIs of P2 are: 2,2,2,2
a)
P1: Cycle Time= 1/2.5x109 = 400 ps
Terefore,
=106* (1*10%+2*20%+3*50%+3*20%)*500x10-12 s
= 106 (260/100)*500* 10-12 s
= 1.3* 10-3 s
P2: Cycle time= 1/3x109 = 333 ps
Therefore,
= 106* (2*10%+2*20%+2*50%+2*20%)*333x10-12 s
= 106 (200/100)*333x10-12
= 0.66* 10-3 s
So that,P2 is faster
b)
P1: Cycle Time= 1/2.5x109 = 400 ps
Terefore,
=106* (1*10%+2*20%+3*50%+3*20%)*500x10-12 s
= 106 (260/100)*500* 10-12 s
= 1.3* 10-3 s
P2: Cycle time= 1/3x109 = 333 ps
Therefore,
= 106* (2*10%+2*20%+2*50%+2*20%)*333x10-12 s
= 106 (200/100)*333x10-12
= 0.66* 10-3 s
c)
For P1, total number of clock cycles: 106* (1*10%+2*20%+3*50%+2*20%) = 2.6*106
For P2, total number of clock cycles: 106* (2*10%+2*20%+2*50%+2*20%) = 2*106