I only need answer for part (e) QUESTION 3 Datapaths (25 Marks) a) You are provi

Question

I only need answer for part (e)

QUESTION 3 Datapaths (25 Marks) a) You are provided with a logic circuit that performs the following: if C otherwise Out=0. You can assume the inputs X, Y and C and the output Out are each 1- bit wires. It has the following symbol and entity declaration or X>Y, Ou-1; entity greater_than is x, Y in std_logic; Out out std_logic); port ( end greater_than; Draw a schematic that compares two 3-bit numbers A and B. It should return a 1 if A>B otherwise it should return a zero. Your design should consist of 3 instances of the entity above. (5 marks) b) Write VHDL code that represents your schematic from Q3a). You may use the following declaration and the com nt from part Q3a) (7 marks entity greater_than_3bit is X, Y Out in std_logic_vector(2 downto 0); out std_logic ); port ( end greater_than_3bit; c) Let us use the following symbol to represent your answer to Q3a) Out Draw a schematic to find the maximum of two 3-bit numbers A and B. You may use the symbol above, as well as multiplexers and any Boolean logic gates. Try to use as few components as possible. (3 marks) d) Let us use the following symbol to represent your answer to Q3c) (this symbol takes in two 3-bit numbers A and B and returns the larger of the two numbers) max(A,B) Out> Suppose you now wish to create a circuit to find the maximum of 4 3-bit inputs A, B, C and D. To do this, create a schematic that use three instances of the circuit max(A,B) in a parallel fashion. (6 marks) e) Comment on the benefits and limitations of using parallelism as in for Q3d) instead of a sequ ential software-style design (4 marks)

Explanation / Answer

Answer is as follows :

Part e )

Benefits of using parallelism instead of sequential software design :

Limitations of using parallelism instead of sequential software design :

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