CSE 401 Midterm May 15, 2017 1 pipeline (40pt) A particular (fictional) CPU has
ID: 3904045 • Letter: C
Question
CSE 401 Midterm May 15, 2017 1 pipeline (40pt) A particular (fictional) CPU has the following internal units and timings (WR and RR are write/read registers, ALU does all logic and integer nerations and there is a separate floating point unit. ID - instruction fetch and decode 150ps RR - read registers 40ps WR - write registers 60ps ALU - arithmetic and logic 180ps FPU - floating point 280ps MEM-memory access 200ps There are 6 basic instruction types: 1. LOAD: ID+RR+ALU+MEM+WR: 660ps 2. STORE: ID+RR+ALU+MEM: 600ps 3. MEMOP: ID+WR+RR+ALU+MEM: 660ps 4. LOGIC/INTEGER: ID+RR+ALU+WR: 460ps 5. FLOATING POINT: ID+RR+FPU+WR: 560ps 6. BRANCH: ID+RR+ALU: 400ps 1 cycle is 660ps for this machine, on the assumption that all instructions take 1 cycle (ignore memory delays). Outline what a pipeline would look like: Give • number of stages 5 Stages • operations in each stage • new clock rate • speedup compared to original 660ps instruction rate with no pipeline. Assume you double the number of registers, but increased address complexity would add 10ps to RR and 15ps to WR. What (if any) changes would you malee to your pipelined machine (e.g. clock or stages or both)?Explanation / Answer
The CPU should be pipelined as below the six instruction types to support.
1) ID
2) WR
3) RR
4) ALU
5) FPU
6) MEM
7) WR
There are 7 stages available in the processor.
Each Stage
ID - fetches the instruction & decodes it
WR - write the registers
RR - Read the registers
ALU - perform the arithmetic/logic operations
FPU - perform floating point operations
MEM - performs the memory access
WR - write the registers
Clock rate
= 1/1 cycle time
= 1/280 ps
= 3.5 GHz
660 ps instruction comparing speed up with real
Time needed to execute the single instruction = 280 ps
Speed up = 660 / 280
= 2.35
There is no need to make changes in the pipelined machine. When the registers count is doubled and adding extra time to the registers, never affect the clock or stages of the pipelined-processor.