I. ROM Design 1. Requirement Design ROM that has 16 locations each 32 bits wide.
ID: 3910530 • Letter: I
Question
I. ROM Design 1. Requirement Design ROM that has 16 locations each 32 bits wide. The 16 locations have the values like 0xDEADBEEF. 0xCAFEBABE, OxDEADFEED and so on of your choice. There will be a Chip Select (CS) input that activates the chip. The address input to the chip is a vector. The output would also be a vector that should send out the data already initialized at the active clock edge, depending on the address input to the chip. Clk CS Address Data Out 16x32 bits The interface can be as below: entity ROM_32Bits_Design is port C?k:instd cs:instd_logic Address:instd_logic_vector (3downto0) Data_out: outstd_logic_vector (31downto0) logic;Explanation / Answer
A ROM is essentially a memory device in which permanent binary information is stored. The binary information must be specified by the designer and is then embedded in the unit to form the required interconnection pattern. Once the pattern is established it stays within the unit even when power is turned off and on again.
ROM does not have data inputs because it does not have a write operation. Consider for example a 32 x 8 ROM. The unit consists of 32 words of 8 bits each. There are five input lines that form the binary numbers from 0 through 31 for the address. The internal logic construction of the ROM. The five inputs are decoded into 32 distinct outputs by means of a 5 x 32 decoder. Each output of the decoder represents a memory address. The 32 outputs of the decoder are connected to each of the eight OR gates.
In general, a 2k x n ROM will have an internal k x 2k decoder and n OR gates. Each OR gate has 2k inputs, which are connected to each of the outputs of the decoder.
Between the lines is logically equivalent to a switch that can be altered to either be close or open .The programmable intersection between two lines is sometimes called cross point. The internal binary storage of a ROM is specified by a truth table that shows the word content in each address. The Table 1 shows the five inputs under which are listed all 32 addresses. At each address, there is stored a word of 8 bits, which is listed under the outputs columns .The table shows only the first four and the last four words in the ROM. The complete table must include the list of all 32 words.
When the input of the ROM is 00011, all the outputs of the decoder are 0 except for output 3, which is at logic 1. The signal equivalent to logic 1 at decoder output 3 propagates through the connections to the OR gate outputs of A7 , A5, A4 and A1.The other four outputs remain at 0. The result is that the stored word 10110010 is applied to the eight data outputs.