Simulate/ code in verilog: Develop an electronic key system using the FSM (moore
ID: 3913001 • Letter: S
Question
Simulate/ code in verilog: Develop an electronic key system using the FSM (moore) methology. Use from student ID and use the last 4 digits:(0864) if the number is <5 then = 1 if the number is >=5 then = 0 example: 8012345. Take last 4 digits (2345) which makes it 0001. In my case, the last 4 digits are 0864, which makes it 0110 features of FSM (moore FSM): input 4 bits serially, if the sequence is correct, then you proceed to next state. Otherwise, go to error state, then go to rest state Need verilog code Simulate/ code in verilog: Develop an electronic key system using the FSM (moore) methology. Use from student ID and use the last 4 digits:(0864) if the number is <5 then = 1 if the number is >=5 then = 0 example: 8012345. Take last 4 digits (2345) which makes it 0001. In my case, the last 4 digits are 0864, which makes it 0110 features of FSM (moore FSM): input 4 bits serially, if the sequence is correct, then you proceed to next state. Otherwise, go to error state, then go to rest state Need verilog code Simulate/ code in verilog: Develop an electronic key system using the FSM (moore) methology. Use from student ID and use the last 4 digits:(0864) if the number is <5 then = 1 if the number is >=5 then = 0 example: 8012345. Take last 4 digits (2345) which makes it 0001. In my case, the last 4 digits are 0864, which makes it 0110 features of FSM (moore FSM): input 4 bits serially, if the sequence is correct, then you proceed to next state. Otherwise, go to error state, then go to rest state Need verilog codeExplanation / Answer
Following is the verilog code for above algorithm:
// 4-State Moore state machine
// A Moore machine's outputs are dependent only on the current state.
// The output is written only when the state changes. (State
// transitions are synchronous.)
module seq_dect
(
input clk, data_in, reset,
output reg data_out
);
// Declare state register
reg [2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
// Determine the next state
always @ (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)
state <= S1;
else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:
if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;
S4:
if (data_in)
state <= S1;
else
state <= S2;
endcase // case (state)
end // always @ (posedge clk or posedge reset)
// Output depends only on the state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)
endmodule // moore_mac