Pipeline 1) Describe the decode phase. Mention what are the operands of each typ
ID: 3914760 • Letter: P
Question
Pipeline
1) Describe the decode phase. Mention what are the operands of each type of instruction (load, store, r-format, beq) Give the size of the involved inter-stage (phase) registers.
2) Consider the following MIPS assembly code:
sw $s1, 48(%s0)
add $t1, $t2, $t3
beq $s4, $s5 Loop
sub $t4, $s2, $t5
sll $t1, 4
What will be the performance of executing the above 5 instructions in a single-cycle implementation if:
Accessing (using) Memory Units takes: 250 ps
Register File takes: 200 ps
Main ALU takes: 200 ps
Note: accessing the other unit is considered to take no time;
3) Mention the three types of hazards that can occur in pipelining, and give a brief description of them.
Describe the write-through policy and explain the use of it.
4) Find the total number of bytes for a direct mapping cache to store 512KB of data in 4 words blocks assuming a 32-bit address and word addressing. Explain your answer. Note: 1K = 1024
Explanation / Answer
3)Answer:
There are three types of hazards in a pipeline, they are as follows
:•Structural Hazards :
arise from resource conflicts when the hardware cannot support all combinations of instructions simultaneously in overlapped execution.
This situation arises mainly when two instructions require a given hardware resource at the same time and hence for one of the instructions the pipeline needs to be stalled.
The most common case is when memory is accessed at the same time by two instructions. One instruction may need to access the memory as part of the Execute or Write back phase while other instruction is being fetched. In this case if both the instructions and data reside in the same memory. Both the instructions can’t proceed together and one of them needs to be stalled till the other is done with the memory access part. Thus in general sufficient hardware resources are needed for avoiding structural hazards
•Data Hazards:
arise when an instruction depends on the results of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.
A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline. As a result of which some operation has to be delayed and the pipeline stalls.
Whenever there are two instructions one of which depends on the data obtained from the other.
A=3+A
B=A*4
For the above sequence, the second instruction needs the value of ‘A’ computed in the first instruction.
Thus the second instruction is said to depend on the first.
If the execution is done in a pipelined processor, it is highly likely that the interleaving of these two instructions can lead to incorrect results due to data dependency between the instructions. Thus the pipeline needs to be stalled as and when necessary to avoid errors
•Control Hazards:
arise from the pipelining of branches and other instructions that change the PC
The instruction fetch unit of the CPU is responsible for providing a stream of instructions to the execution unit. The instructions fetched by the fetch unit are in consecutive memory locations and they are executed.
However the problem arises when one of the instructions is a branching instruction to some other memory location. Thus all the instruction fetched in the pipeline from consecutive memory locations are invalid now and need to removed(also called flushing of the pipeline).This induces a stall till new instructions are again fetched from the memory address specified in the branch instruction.
Thus the time lost as a result of this is called a branch penalty. Often dedicated hardware is incorporated in the fetch unit to identify branch instructions and compute branch addresses as soon as possible and reducing the resulting delay as a result.
Write-through policy:
Write through is a storage method in which data is written into the cache and the corresponding main memory location at the same time. The cached data allows for fast retrieval on demand, while the same data in main memory ensures that nothing will get lost if a crash, power failure, or other system disruption occurs
Advantage:
- read miss never results in writes to main memory
- easy to implement
- main memory always has the most current copy of the data (consistent)