For the following assume that values A, B, C, D, E and F reside in memory. Also
ID: 441454 • Letter: F
Question
For the following assume that values A, B, C, D, E and F reside in memory. Also assume that instruction operation codes are represented in 8 bits, memory addresses are 64 bits, and register addresses are 6 bits. For each instruction set architectures (will follow), how many addresses, or names, appear in each instruction for the code to compute C = A + B, and what is the total code size? Instruction set architectures: Stack: Push A, Push B, Add, Pop C Accumulator: Load A, Add B, Store C Register (register-memory): (Load R1, A), (Add R3, R1, B), (Store R3, C) Register (load-store): (Load R1, A), (Load R2,B), (Add R3, R1, R2), (Store R3,C) *parentheses are only to show separation between itemsExplanation / Answer
Stack
Accumulator
Register (register-memory)
Register (load-store)
Push A
Push B
Add
Pop C
Load A
Add B
Store C
Load R1,A
Add R3,R1,B
Store R3,C
Load R1,A
Load R2,B
Add R3,R1,R2
Store R3,C
Figure A.2The code sequence for ``C = A + B`` for four classes of instruction sets.Note that theAddinstruction has implicit operands for stack and accumulator architectures and explicit operands for register architectures. It is assumed that A, B, and C all belong in memory and that the values of A and B cannot be destroyed. Figure A.1 shows theAddoperation for each class of architecture.
Stack
Accumulator
Register (register-memory)
Register (load-store)
Push A
Push B
Add
Pop C
Load A
Add B
Store C
Load R1,A
Add R3,R1,B
Store R3,C
Load R1,A
Load R2,B
Add R3,R1,R2
Store R3,C