The code below is not compiling due to undefined operation. Can anyone figure th
ID: 644887 • Letter: T
Question
The code below is not compiling due to undefined operation. Can anyone figure this out? Please help... Thank you.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity add4bit is
Port ( AI : in STD_LOGIC_VECTOR (3 downto 0);
BI : in STD_LOGIC_VECTOR (3 downto 0);
SEL : in STD_LOGIC;
SO : out STD_LOGIC_VECTOR (4 downto 0));
end add4bit;
architecture Behavioral of add4bit is
begin
process
begin
if(SEL='0') then
SO<= AI + BI;
else
SO<= AI - BI;
end if;
end process;
end Behavioral;
Explanation / Answer
if(SEL='0') then ------------>Here one error if(SEL=='0')