Status flags. Sometimes it is necessary for a digital computer to know whether a
ID: 670003 • Letter: S
Question
Status flags. Sometimes it is necessary for a digital computer to know whether a number stored in a register is zero, positive non-zero, or negative. A positive number would have its most significant bit equal to 0 and the remaining bits not all 0s. A zero would have all bits 'equal to 0. A negative number would have its most significant bit equal to 1. In order to make the problem manageable at this level, you may assume that registers are only three bits long. Design a circuit, using only NAND gates, to detect whether the number in the register is zero, positive, or negative. A block diagram of the system is shown below. Assume that x is the most significant bit. Try to use as few IC packages as possible. (Hint: think of sharing logic gates among the three functions.)Explanation / Answer
Design
NAND Gate
NAND and NOR gates are generally faster and use fewer components than AND or OR gates.
• Any logic function can be implemented using only NAND gates or only NOR gates.
NAND gate or NOR gate forms a functionally completeset since any switching function can be expressed in terms of NAND gate or NOR gate.
• Similarly, the set AND, OR, and NOT forms a functionally complete set since any Boolean
function can be expressed in terms of SOP and POS using only the AND, OR, and NOT
operations
Sometimes when you're building circuits, you dont always have the right components. Fortunately when it comes to digital logic gates, you can make the component you need If you're fresh out of NOT gates, but have an extra NAND gate laying around, you're in luck With a NAND gate you can connect the two inputs, then add your input, to effectively create a NOT gate Its as simple as that! See picture for circuit diagram.
Design of 2-Level Circuits using NAND and NOR Gates
• Procedure for designing a minimum 2-level NAND-NAND circuit
1. Find a minimum SOP expression for F.
2. Draw the corresponding 2-level AND-OR circuit.
3. Replace all gates with NAND gates leaving the gate interconnections unchanged. If theoutput gate has any single literals as inputs, complement these literals