CS 461 Operating System Project: The simulation is to be named SYSTEM. SYSTEM wi
ID: 671632 • Letter: C
Question
CS 461 Operating System Project:
The simulation is to be named SYSTEM. SYSTEM will consist of three major subsystem called LOADER, MEMORY, and CPU. The naming conventions must be strictly followed.
An ERROR-HANDLER subsystem is required for warnings and errors. For illegal opcode, memory range fault, illegal user input, suspected infinite job, program size too large, illegal trace flag, etc., appropriate error code (as the error or warning number/code). This subsystem will generate the appropriate error/warning message, which may be classified into load-time, decoding-time, memory- reference, execution-time, etc. An error is “fatal” in that it stops execution, a warning is not fatal.
The simulation (the operating SYSTEM) will invoke the LOADER to (1) read and load “user programs” into memory, and (2) call CPU to execute them. The CPU subsystem will return to the SYSTEM) if (a) a fatal error occurs, (b) an input/output operation is requested, or (c) a Halt is executed. If (a) or(c) occurs, the SYSTEM will clear the job from the SYSTEM and read and load the next job in the “batch”, if any, If (b) occurs, the SYSTEM will idle until the input/ output operation is completed (10 virtual time units, 2 for the instruction itself and 8 for the actual input/ output), and then the SYSTEM will return to the CPU. In this step, the input/output of “user programs” will be done at the terminal via standard I/O, i.e., keyboard for input and screen for output, the user job output is to be the output file as well (see below).
I. MEMORY subsystem
MEMORY(X, Y, Z)
Where X = “READ” or “WRIT” or “DUMP” (X is the control signal)
Y = memory address (Y is the mem. add. reg.)
Z = variable to be written or read into (Z is the mem. buf. reg.)
An array (called MEM) is to be used to simulate the computer system’s memory. Its subscripts will range from 0 to FF. Any reference outside this range will cause a MEMORY ADDRESS FAULT message to be generated.
If X has the value “WRIT”, the contents of Z will be written in MEM[Y].
If X has the value “READ”, the contents of MEM[Y] will be written in Z.
If X has the value “DUMP”, the contents of the physical memory will be output as follows (all in hexadecimal):
0000 word0 word1 word2 word3 word4 word5 word6 word7 0008 word8 word9 word0A word0B word0C word0D word0E word0F 0010 word10 word11 word12 word13 word14 word15 word16 word17
Note: No other subsystem, except the LOADER, is allowed to reference the array called MEM.
II. LOADER subsystem
LOADER (starting address, trace switch)
The loader loads information in record format. The record formats are:
First Record Location (2 digits) (1 blank) Length (2 digits) Data Record 32 hex (hexadecimal) digits specifying 4 words of information Last Record Start Address (2 digits) (1 blank) Trace Flag (1 digit)
Location is the memory address of the first memory words to be loaded. Length is the number of memory to be loaded. The data records specify the value to be loaded into successive memory words, The Start Address and Trace Flag will be returned in the parameters of the LOADER subsystem. Location, Length, Start Address, and the data records will all be in Hex. If deemed necessary, a procedure HEXBIN may be written to convert a string of 8 Hex digits to one 32-bit binary value. The loader has a buffer (one or more registers of size 32 bits each).
III.CPU subsystem
CPU(X, Y)
Where X is the initial value of the program counter (PC) and
Y is the trace switch (0 = trace off ad 1 = trace on)
The CPU subsystem will loop indefinitely until a Halt instruction, an illegal instruction, or an input/output instruction is interpreted.
The computer system has the following instruction format.
I OP A B DADDR
1 7 4 4 , 16 <------------- number of bits in each field
Where I denotes indirect addressing (one level only),
OP is the operation code,
A denotes the arithmetic register (accumulator),
B denotes the index register,
DADDR denotes the address of an operand,
And B = 0 indicates no indexing, and indirect addressing is performed before indexing.
The operation codes to be simulated follow.
OPERATION CODE FUNCTION SEMATICS
HLT 00 Halt Stop execution
LD 01 Load C(EA)-->REG
ST 02 Store C(REG)-->EA
AD 03 Add C(REG)+ C(EA)-->REG
SB 04 Subtract C(REG)- C(EA)-->REG
MPY 05 Multiply C(REG)* C(EA)-->REG
DIV 06 Divide C(REG)/ C(EA)-->REG
SHL 07 Shift left C(REG) Shift left EA place(no wrap- around)
SHR 08 Shift right C(REG) Shift Right EA place(no wrap- around)
BRM 09 Branch on minus If C(REG)<0 then EA-->PC
BRP 0A Branch on plus If C(REG)>0 then EA-->PC
BRZ 0B Branch on zero If C(REG)=0 then EA-->PC
BRL 0C Branch and link C(PC)--> REG; EA--> PC
AND 0D And C(REG)& C(EA)-->REG
OR 0E Or C(REG)| C(EA)-->REG
RD 0F Read 32 hex digits (4 words of initial data) from “sysin” -->EA to EA+3
WR 10 Write C(EA) to C(EA+3)-->”sysout” (32 Hex digits)
DMP 11 Dump memory Dump physical memory to sysout
Note: The 4-word I/O is presumably an I/O channel block-transfer restriction; appropriate 0 padding can be used to fill the gaps. C(X) refers to the contents of X. EA (effective address) refers to a memory location. REG refers to a register. There are 16 32-bit registers numbered from 0 to 1510. EA is the effective address after indirect addressing and index addressing.
with indirect addressing EA = C(DADDR)
with index addressing EA = C(INDEX) + DADDR
with both EA = C(INDEX) + C(DADDR)
If the trace flag is on, the CPU subsystem will generate the following: PC, Instruction, Contents of A before execution, and Content of A and EA after execution.
An error message is to be generated and a Halt is to be executed if a CPU error (such as divided by zero or illegal opcode) occurs.
Include a variable CLOCK in your SYSTEM (i.e., in your simulation). Increment the CLOCK by 1 virtual time until for every non-input/output instruction executed except MPY, DIV, and BRL for which the increment is to be 2 virtual time units. Output the value of CLOCK at the end of each user program,
IV. Test “data”
Test program 1:
The program as it is listed below is in the toy assembly language given above. Note that the “program” is fully documented. Following the program is the loader format which is the load module that will be used as “input” to your simulation.
; This test job prints the factorial of a number. The program
; loads the number into a register and keeps multiplying
; it with another register containing the (cumulative)
; resulting factorial, decreasing it by one, and repeating
; until the original number becomes 0. The final factorial
; value is then stored at location FACT and finally 4 words of
; information starting at FACT is printed using WR.
START RD, INFO ; read 4 words into INFO
LD, 2, ONE ; load ONE into REG 2
LD, 1, INFO ; load INFO into REG 1
BRZ, 1, PR ; if INFO = 0, goto PR
BRM, 1, PR
BACK ST, 1, I ; store contents of REG 1 into I
MPY,2, I ; multiply REG 2 contents by I
SB, 1, ONE ; subtract ONE from REG 1 contents
BRP,1, BACK ; if REG 1 contents >0, goto BACK
PR ST, 2, FACT ; store final answer of REG 2 in FACT
WR, FACT ; write 4 words beginning at FACT
HLT ; halt
ONE 1
I 0
INFO 0
N 0
BLK 0
FACT 0
00 18
0F00000E0120000C0110000E0B100009
091000090210000D0520000D0410000C
0A100005022000141000001400000000
00000001000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00 0
Test program 2(Bonus points 20%): Write as small a program as you can (in the toy assembly language provided, followed by its translation into the loader format) to set every word of memory to a value equal to is address. The last instruction should be DUMP HLT. There may be a few which you cannot set.
1. Cumulative job identification number (this number id reset each time that you start your operating system simulation).This should be one for this step since your simulation will handle exactly one “user job” each time that you run it (the reason being the absence of a memory manager and a scheduler, and lack of a JCL in assignment 1).
2. Warning messages if necessary/ appropriate.
3. A message indicating the nature of termination (normal or abnormal, plus a descriptive error message if abnormal). 4. Output of the current user job resulting from the execution of the WR instruction (if job terminated normally).
5. CLOCK value in hex at termination.
6. Run time for the job in decimal, probably subdivided into execution time, input/output time, etc, Note that all “times “refer to virtual time periods as measured by differences between values if the simulated system’s CLOCK
Explanation / Answer
Solution :
GENERATE
*
* GENERATE A WORD OF LOADER OUTPUT.
* THE LOADER WORD IS IN VALUE. REGISTER I6 HAS
* THE ADDRESS OF THE LOCATION WHERE IT SHOULD
* BE LOADED. IF THIS WORD IS A CONTINUATION
* OF THE CURRENT BUFFER, IT IS SIMPLY STORED.
* IF THE WORD IS NONCONTIGUOUS OR FILLS THE
* BUFFER, THE BUFFER IS EMPTIED.
*
GNSAVEA ORIG *+1
*
GENERATE STJ GENEXIT
STA GNSAVEA
ST1 GNSAVE1(0:2)
* CMP6 NXTLOADLOC CHECK IF CONTIGUOUS
JNE FINISHBLCK IF NOT, FINISH OLD BLOCK
* LD1 LDRBLOCK(4:5) NUMBER OF WORDS
INC1 1
ST1 LDRBLOCK(4:5)
* LDA VALUE
STA LDRBLOCK,1 STORE GENERATED WORD
* INC6 1 INCREASE LOCATION COUNTER
ST6 NXTLOADLOC
* CMP1 BLCKLENGTH CHECK FOR END OF BLOCK
JGE FINISHBLCK IF SO, FINISH BLOCK
LDA GNSAVEA
GNSAVE1 ENT1 * RESTORE REGISTER
GENEXIT JMP *
*
*
* SUBROUTINE FINISHBLCK
*
* OUTPUT TO THE LOADER THE BLOCK IN LDRBLOCK.
* NUMBER OF WORDS IS IN BYTE 4:5 OF FIRST WORD.
* (MAY BE ZERO, IN WHICH CASE IGNORE CALL).
* COMPUTE CHECKSUM AND OUTPUT IT TOO
*
CHECKSUM ORIG *+1
FLBSAVEA ORIG *+1
FINISHBLCK STJ FLBEXIT
STA FLBSAVEA
ST1 FLBSAVE1(0:2)
*
LD1 LDRBLOCK(4:5)
J1Z FLBQUIT IF BLOCK IS EMPTY
*
STZ CHECKSUM INITIALIZE CHECKSUM
ENT1 0 INDEX AND COUNTER
*
BLOCKOUT LDA LDRBLOCK,1
JMP TAPEOUT OUTPUT EACH WORD
ADD CHECKSUM(1:5)
STA CHECKSUM(1:5) AND COMPUTE CHECKSUM
*
INC1 1
CMP1 LDRBLOCK(4:5) CHECK ALL WORD OUT
JLE BLOCKOUT
*
LDA CHECKSUM(1:5) OUTPUT CHECKSUM
JMP TAPEOUT
*
JOV *+1 TURN OVERFLOW OFF (IF ON)
*
FLBQUIT STZ LDRBLOCK NEW HEADER WORD
ST6 LDRBLOCK(0:2)
*
LDA FLBSAVEA RESTORE REGISTERS
FLBSAVE1 ENT1 *
FLBEXIT JMP *
*