Design a 16-bit Logic Unit with A, B, and Opcode as inputs and LogicOut as outpu
ID: 1715974 • Letter: D
Question
Design a 16-bit Logic Unit with A, B, and Opcode as inputs and LogicOut as output. This design performs logical operations: A and B, A or B, A nand B, A nor B, A xor B, A xnor B, Not A, and Not B. This 16-bit Logic Unit has the following entity:
entity LogicUnit16bit is Port( A : IN std_logic_vector(15 downto 0); -- Input
B : IN std_logic_vector(15 downto 0); -- Input
OpCode : IN std_logic_vector(2 downto 0); -- op select
LogicOut : OUT std_logic_vector(15 downto 0)); -- Output
end LogicUnit16bit;
Design a test bench to verify the functionality of your design. All possible operations should be included in the test bench and shown in the simulation waveform.
Subject: Digitial System Design
Explanation / Answer
ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LogicUnit16bit is Port( A : IN std_logic_vector(15 downto 0); -- Input
B : IN std_logic_vector(15 downto 0); -- Input
OpCode : IN std_logic_vector(2 downto 0); -- op select
LogicOut : OUT std_logic_vector(15 downto 0)); -- Output
end LogicUnit16bit;
architecture alu3 of LogicUnit16bit is
begin
process(A,B,OpCode)
begin
case OpCode is
when "00"=>
LogicOut <= A and B;
when "01"=>
LogicOut <=A or B;
when "10"=>
OpCode <=A nand B;
when "11"=>
LogicOut <=not A;
when others =>
LogicOut <=not B;
end case;
end process;
end alu3;