Design a 16-bit Logic Unit with A, B, and Opcode as inputs and LogicOut as outpu
ID: 1716171 • Letter: D
Question
Design a 16-bit Logic Unit with A, B, and Opcode as inputs and LogicOut as output. This design performs logical operations: A and B, A or B, A nand B, A nor B, A xor B, A xnor B, Not A, and Not B. This 16-bit Logic Unit has the following entity: entity LogicUnit16bit is Port( A : IN std_logic_vector(15 downto 0); -- Input B : IN std_logic_vector(15 downto 0); -- Input OpCode : IN std_logic_vector(2 downto 0); -- op select LogicOut : OUT std_logic_vector(15 downto 0)); -- Output end LogicUnit16bit; Below table describes the behavior of 16-bit Logic Unit
Design a test bench to verify the functionality of your design. All possible operations should be included in the test bench and shown in the simulation waveform.
DIGITAL SYSTEM DESIGN
Opcode (2 downto 0) Operation nor 001 010 011 100 101 110 A nand B or A and B xor A xnor B Not A Not BExplanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LogicUnit16bit is
port(
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
OpCode : in STD_LOGIC_VECTOR(2 downto 0);
LogicOut : out STD_LOGIC_VECTOR(15 downto 0);
);
end LogicUnit16bit;
architecture temp of LogicUnit16bit is
begin
mux : process (A,B,OpCode) is
begin
if (OpCode="0000") then
LogicOut <= A nor B;
elsif (OpCode="001") then
LogicOut <= A nand B;
elsif (OpCode="010") then
LogicOut <= A or B;
elsif (OpCode="011") then
LogicOut <= A and B;
elsif (OpCode="100") then
LogicOut <= A xor B;
elsif (OpCode="101") then
LogicOut <= A xnor B;
elsif (OpCode="110") then
LogicOut <= not A;
else
dout <= not B;
end if;
end process mux;
end temp;