Design a 16-bit register (with synchronous reset) that has the following entity:
ID: 1716058 • Letter: D
Question
Design a 16-bit register (with synchronous reset) that has the following entity:
entity Reg16bit is
Port( A : IN std_logic_vector(15 downto 0); -- Input
Load : IN std_logic; -- Load the input value when Load=‘1’
Clock : IN std_logic;
Reset : IN std_logic; -- Reset the value of the register
RegOut: OUT std_logic_vector (15 downto 0));
end Reg16bit;
In your test bench show that your register is loading the input value only at Load = 1 and not at Load = 0; your register is storing the value inside, when loaded, without
changing it; and your register value is reset to “0000_0000” whenever the reset is set to 1.
Report: VHDL code
SUBJECT: DIGITAL SYSTEM DESIGN
Explanation / Answer
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY reg_example IS PORT(
Port( A : IN std_logic_vector(15 downto 0); -- Input
Load : IN std_logic; -- Load the input value when Load=‘1’
Clock : IN std_logic;
Reset : IN std_logic; -- Reset the value of the register
RegOut: OUT std_logic_vector (15 downto 0));
ARCHITECTURE rt1of reg_exaple IS
BEGIN
Process (clk)
BEGIN
IF rising_edge(clk) THEN
IF load= ‘1’then
Regout=portA;
End IF;
End IF;
END process;
END ARCHITECTURE;