Design a 16-bit register (with synchronous reset) that has the following entity:
ID: 1716118 • Letter: D
Question
Design a 16-bit register (with synchronous reset) that has the following entity:
entity Reg16bit is
Port( A : IN std_logic_vector(15 downto 0); -- Input
Load : IN std_logic; -- Load the input value when Load=‘1’
Clock : IN std_logic;
Reset : IN std_logic; -- Reset the value of the register
RegOut: OUT std_logic_vector (15 downto 0));
end Reg16bit;
In your test bench show that your register is loading the input value only at Load = 1 and not at Load = 0; your register is storing the value inside, when loaded, without changing it; and your register value is reset to “0000_0000” whenever the reset is set to 1.
Note: please provide me with the vhdl code for module and vhdl code for test bench
Subject: Digitial System Design
Explanation / Answer
entity Reg16Bit is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
Load : in STD_LOGIC;
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
RegOut : out STD_LOGIC_VECTOR (15 downto 0));
end Reg16Bit;
architecture Behavioral of Reg16Bit is
begin
PROCESS(CLK,Loas,Reset,A)
variable reg:STD_LOGIC_VECTOR (15 downto 0);
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
if(Reset='1')then
reg:="0000000000000000";
elsif(Load='1')then
reg:=A;
else
reg:=reg;
end if;
end if;
RegOut<=reg;
end process;
end Behavioral;